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Verification condition generator

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A verification condition generator is a common sub-component of an automated program verifier that synthesizes formal verification conditions by analyzing a program's source code using a method based upon Hoare logic. VC generators may require that the source code contains logical annotations provided by the programmer or the compiler such as pre/post-conditions and loop invariants. VC generators are often coupled with SMT solvers in the backend of a program verifier. After a verification condition generator has created the verification conditions they are passed to an automated theorem prover, which can then formally prove the correctness of the code.

Methods have been proposed to use the operational semantics of machine languages to automatically generate verification condition generators. [1]

  1. ^ "Verification Condition Generation via Theorem Proving" (PDF). {{cite web}}: Unknown parameter |authors= ignored (help); line feed character in |title= at position 33 (help)
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