Talk:Prefetch buffer

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Prefetch buffer not improved

um, have to point out that the prefetch buffer is not 'improved' with subsequent generations of DDR...as your other articles on DDR/DDR2/DDR3 indicate, latency is greater which is not an 'improvement'.

Relate to cache

Can the article explain some relation to cache memory or cache operations? —Preceding unsigned comment added by 187.66.85.35 (talk) 00:23, 8 March 2011 (UTC)[reply]

Prefetch buffers are entirely independent of cache. If a read is satisfied from a level of cache closer to the processor, then it won't reach the prefetch buffer. --David-Sarah Hopwood ⚥ (talk) 04:30, 29 July 2012 (UTC)[reply]

The article says 64 bit (4 bytes) word is read from ram, but actually an entire cache line is read in case of a cache miss. So, more like 64 bytes, common for a cache line. In this case size of the prefetch buffer is important - memory is always accessed in bigger chunks. 83.8.27.220 (talk) 08:42, 31 May 2013 (UTC)[reply]