NMOS logic

NMOS logic uses n-type metal-oxide-semiconductor field effect transistors to impliment logic gates and other digital circuits.

The n-type MOSFETs are arranged in a so-called "pull-down network" (PDN) between the output and low-voltage rail, while a resistor is placed between the output and the high-voltage rail. The circuit is designed such that if the desired output is low, then the PDN will be active, creating an electrical connection between the low-voltage rail and the output.

As an example, here is a NAND gate in NMOS logic. Note how the output will be high only if both inputs A and B are low, so that both transistors are "off", i.e. non-conductive.

          _A_
       __|   |__
 low__|         |___ ___R__hi
      |   _B_   |   |
      |__|   |__|   |
                   out

While NMOS logic is very easy to design and manufacture (a MOSFET can be made to opperate as a resistor, so the whole circuit can literally be made with one type of component), it has several shotcomings as well. The worst is that NMOS circuits are very slow to transition from low to high. When transitioning from high to low, the transistors provide very low resistance, and the capacitance of the output drains away very quickly. But the resistance between the output and high is much greater, so the transition takes much longer. Additionally, this asymetric behavior makes NMOS circuits more susceptable to noise. These disadvantages are why most high-speed logic circuits, such as in microprocessors, are built using CMOS logic.