Interrupt
In computing, an interrupt is an asynchronous signal from hardware or software indicating the need for attention. A hardware interrupt causes the processor to save its state of execution via a context switch, and begins execution of an interrupt handler. Software interrupts are usually implemented as instructions in the instruction set, which cause a context switch to the interrupt handler similarly to a hardware interrupt. Interrupts are a commonly used technique for computer multitasking, especially in real-time computing. Such a system is said to be interrupt-driven.
The act of interrupting is referred to as an interrupt request.
Overview
Interrupts originated as a way to avoid wasting the processor's valuable time in polling loops, waiting for external events. Instead, an interrupt signals the processor when an event occurs, allowing the processor to process other work while the event is pending.
Interrupts may be implemented in hardware as a distinct system with control lines, or they may be integrated into the memory subsystem. If implemented in hardware, a Programmable Interrupt Controller (PIC) or Advanced Programmable Interrupt Controller (APIC) is connected to both the interrupting device and to the processor's interrupt pin. If implemented as part of the memory controller, interrupts are mapped into the system's memory address space.
Interrupts can be categorized into the following types: software interrupt, maskable interrupt, non-maskable interrupt (NMI), interprocessor interrupt (IPI), and spurious interrupt. A software interrupt is an interrupt generated within a processor by executing an instruction. Examples of software interrupts are system calls. A maskable interrupt is essentially a hardware interrupt which may be ignored by setting a bit in an interrupt mask register's (IMR) bit-mask. Likewise, a non-maskable interrupt is a hardware interrupt which typically does not have a bit-mask associated with it allowing it to be ignored. An interprocessor interrupt is a special type of interrupt which is generated by one processor to interrupt another processor in a multiprocessor system. A spurious interrupt is a hardware interrupt which is generated by system errors, such as electrical noise on one of the PICs interrupt lines.
Processors typically have an internal interrupt mask which allows software to ignore all external hardware interrupts while it is set. This mask may offer faster access than accessing an IMR in a PIC, or disabling interrupts in the device itself. In some cases, such as the x86 architecture, disabling and enabling interrupts on the processor itself acts as a memory barrier, in which case it may actually be slower.
The phenomenon where the overall system performance is severely hindered by excessive amounts of processing time spent handling interrupts is called an interrupt storm or live lock.
Typical uses
Typical interrupt uses include the following: system timers, disks IO, power-off signals, and traps. Other interrupts exist to transfer data bytes using UARTs or Ethernet; sense key-presses; control motors; or anything else the equipment must do.
A classic system timer interrupt interrupts periodically from a counter or the power-line. The interrupt handler counts the interrupts to keep time. The timer interrupt may also be used by the OS's task scheduler to reschedule the priorities of running processes. Counters are popular, but some older computers used the power line frequency instead, because power companies in most Western countries control the power-line frequency with an atomic clock.
A disk interrupt signals the completion of a data transfer from or to the disk peripheral. A process waiting to read or write a file starts up again.
A power-off interrupt predicts or requests a loss of power. It allows the computer equipment to perform an orderly shutdown.
Interrupts are also used in typeahead features for buffering events like keystrokes.
See also
- Advanced Programmable Interrupt Controller
- Programmable Interrupt Controller
- Inter-Processor Interrupt
- Interrupt Handler
- Interrupt Latency
- Non-Maskable Interrupt