Parallax Propeller

The Parallax Propellor is a 32bit microcontroller with 8 CPU cores. It was introduced in 2006 and has a unique architecture.

Each of the eight 32bit cores has an elementary ALU--divide instructions are not available in assembly at this time--and each core has access to 512 "Longs" of instructions and data, self modifying code is possible. Access to the 32kb memory and to the pins of the 32bit PortA is controlled in round-robin fashion by a internal bus controller called the Hub. The Hub is fixed function.

The initial release runs at up to 80Mhz, and when running the proprietary interpreted SPIN language, 4 clock ticks are required per instruction, giving 8 (from the eight 32bit cores) times 20MHz for 160 million high level instructions per second.

The initial packaging of the chip provided one 32 bit port in a 40pin 0.6in DIP chip. Each of the 8 cores could access the 32bit port A in turn, though generally a core handling serial UART duties would need only 2 or 3 of the pins for Rx, Tx, and possibly handshaking duties, and another core with another task would be assigned several more pins, and so on. It is always possible for each core to access all 32 pins 20 million times a second if need be.

Further developments planned for the packaging of the inital silicon version are a second 32bit port, and various surface mount packagings.

Follow on silicon versions will execute SPIN instructions in a single clock cycle, permit higher clock rates, and may include additional 32bit cores--16 are possible.