Sequential logic circuit
Sequential circuits are logical circuit whose output depends on the past input. These circuit use current input variables and previous input variables by storing the information and putting back into the circuit on the next clock (activation) cycle. Thease circuit are time dependent .A Sequential circuit is connection of flip-flop,feedback circuit and gates.
There are two types of input to the combinational logic; External inputs which come from outside the circuit design and are not controlled by the circuit; Internal inputs which are a function of a previous output states. The internal inputs and outputs are refered to as "secondaries" in the course notes. Secondary inputs are state variables produced by the storage elements, where as secondary outputs are excitations for the storage elements.
Two Main Types of Sequential Circuits
There are two types of sequential circuit,
synchronous and asynchronous
. Synchronous circuit use the flip flop and there status can change only at discrete instant.It use pulsed or level inputs and a clock input to drive the circuit (with restrictions on pulse width and circuit propagation).A clock cab have two state either active or inactive state.
Asynchronous circuit may be regared as combinational circuit with feedback path .Asynchronous circuits do not use a clock signal as synchronous circuits do. Instead the circuit is driven by the pulses of the inputs. You will not need to know anymore about asynchronous circuits for this course.
A pulsed output (as used in the block diagrams above) is an output that lasts for the duration of a particular input pulse but can be less in some cases. For the clocked sequential circuits, the output pulse is the same duration as the clock pulse. A level output refers to an output that changes state at the start of an input pulse or clock pulse and remains in that state until the next input or clock pulse.
Important Sequential Logic Design Issue
An important thing to note with sequential circuits is that duration of the activating pulse should be low enough so that the secondary inputs do not change state in same activating pulse. Allowing the clock pulse to be too long would result in incorrect circuit function, as there will be two different secondary input values for one clock cycle and therefore lead to potentially two state changes in one clock. It would be benefical to have our storage elements to be edge triggered, as this would mean that the clock pulse can be as long as we would like it to be and the circuit would behave in the same way. This is why flip-flops are used as they are edge triggered storage devices.