Microarchitecture simulation
This sandbox is in the article namespace. Either move this page into your userspace, or remove the {{User sandbox}} template. Microarchitecture simulation is an important technique in computer architecture research and computer science education. It is a tool for modeling the design and behavior of a microprocessor and its components, such as the ALU, cache memory, control unit, and data path, among others. The simulation allows researchers to explore the design space as well as to evaluate the performance and efficiency of novel microarchitecture features. For example, several microarchitecture components, such as branch predictors, re-order buffer, and trace cache, went through numerous simulation cycles before they become common components in contemporary microprocessors of today. In addition, the simulation also enables educators to teach computer organization and architecture courses with hand-on experiences.
Classification
In this section, the microarchitecture simulation is classified into multiple categories according to input types and level of details. Specifically, the input can be a trace collected from an execution of program on a real microprocessor (so called trace-driven simulation[1]) or a program itself (so called execution-driven simulation[2]). The selection of input types for simulation is a trade-off between space and time. In particular, a very detailed trace for a highly accurate simulation requires a very large storage space, whereas a very accurate execution-driven simulation takes a very long time to execute all instructions in the program. Apart from input types, the level of details can also be used to classify the simulation. In particular, a piece of software that simulates a microprocessor executing a program on a cycle-by-cycle basis is known as cycle-accurate simulator, whereas instruction set simulator only models the instruction scheduling and coarse timing of the microprocessor executing a program.
Examples
- Shade[3] (trace-driven, instruction set simulator)
- SimpleScalar[4] (execution-driven, cycle-accurate simulator)
- SMTSIM[5] (execution-driven, cycle-accurate simulator)
References
- ^ Uhlig, R. A., & Mudge, T. N. (2004). Trace-Driven Memory Simulation: A Survey. ACM Computing Surveys, 29(2), 128-170.
- ^ Burger, D., & Austin, T. M. (1997). The Simplescalar Tool Set Version 2.0. Computer Architecture News, 25(3), 13-25.
- ^ Cmelik, R. F., & Keppel, D. (1994). Shade: A Fast Instruction-Set Simulator for Execution Profiling. ACM SIGMETRICS Performance Evaluation Review, 22(1), 128-137.
- ^ Austin, T., Larson, E., & Ernst, D. (2002). SimpleScalar: An Infrastructure for Computer System Modeling. IEEE Computer Magazine, 35(2), 59-67.
- ^ Tullsen, D. M. (1996). Simulation and Modeling of a Simultaneous Multithreading Processor. In Proceedings of the 22nd Annual Computer Measurement Group Conference.