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Circuit design language

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This is an old revision of this page, as edited by BD2412 (talk | contribs) at 20:40, 20 October 2012 (minor fixes, mostly disambig links, replaced: CalibreCalibre using AWB). The present address (URL) is a permanent link to this revision, which may differ significantly from the current revision.

Circuit design language is a circuit schematic has been extracted to a CDL netlist for electronic circuit simulation.

Several vendors such as Cadence Design Systems, Calibre, and Synopsys support CDL netlists, although their solutions may be proprietary and not readable by competing systems.