Open Verification Methodology
The Open Verification Methodology (OVM) is a documented methodology with a supporting building-block library for the verification of semiconductor chip designs. The initial version, OVM 1.0, was released in January, 2008,[1] and regular updates have expanded its functionality. The latest version is OVM 2.1.2, released in January, 2011. The current release and all previous releases are available, under the Apache License, on the OVM World[2] site.
The reuse concepts within the OVM were derived mainly from the URM (Universal Reuse Methodology) which was, to a large part, based on the eRM (e Reuse Methodology) for the e Verification Language developed by Verisity Design in 2001. The OVM also brings in concepts from the AVM (Advanced Verification Methodology (AVM). The UVM class library brings much automation to the SystemVerilog language such as sequences and data automation features (packing, copy, compare) etc. The UVM also has recommendations for code packaging and naming conventions.
The OVM has won recognition from Electronic Design[3] and a DesignVision award from the International Engineering Consortium.[4]
The OVM was co-developed by Mentor Graphics and Cadence Design Systems, and they continue to guide its evolution in concert with the nine user companies of the OVM Advisory Group.[5] The OVM is publicly supported by more than 60 partner companies[6] offering tools, training, and services.
The OVM was standardized within Accellera, which voted to make it the basis for the Universal Verification Methodology (UVM).[7] Accellera released version UVM 1.0 EA on May 17, 2010 [8]..