Talk:Diode–transistor logic

Misleading statement in operation section?

Two diodes in series are commonly used to lower the voltage and prevent any base current when one or more inputs are at low logic level.

Two diodes in series double the voltage, not lower it. It's not clear at all to me from this description how 2 diodes could improve the turnoff of the transistor base (one in the transistor emitter might). Gareth8118 (talk) 12:54, 6 March 2008 (UTC)

I suspect that was meant to describe an added diode as shown here. Maybe you can fix it. Dicklyon (talk) 15:57, 6 March 2008 (UTC)

Simplified schematic

It should be emphisized that the diagram is a "Simplified schematic" and does not actually work. Someone should be able to find a "published" schematic that actually works. I can only provide a design similar to those used in early computer designs. I would hate to think that some future engineer would try to build the circuit as shown and find that he wasted his time. UPCMaker (talk) 22:59, 3 April 2008 (UTC)

I replaced it with a correct one; not quite as simple, but shows a resistor configuration that will make it work. From the GE Transistor Manual (3rd through 6th editions). Dicklyon (talk) 04:53, 4 April 2008 (UTC)

This is great! You might add a capacitor across R3 which was common for DTL to reduce saturation delay. That was one of the main reasons DTL was faster than RTL. TTL could not allow a speed up capacitor because it would need one on each input resistor and that would have coupled noise from input to input. UPCMaker (talk) 00:10, 5 April 2008 (UTC)

Sorry about my comments added to the switching circuits. I just wish someone would fix all the errors and miss statements that I guess come from bad publications. We had the DTL schematic fixed but it went back to the bad one. If someone that was doing the work can't comment then can't someone try to research these circuits.UPCMaker —Preceding unsigned comment added by 206.53.104.196 (talk) 12:12, 25 October 2009 (UTC) Italic text —Preceding unsigned comment added by 210.212.253.106 (talk) 08:13, 18 November 2009 (UTC)

CTDL

I propose creating an article for CTDL for reasons of consistency. Information about CTDL is already part of this article under the section called "CTDL". I looked at http://en.wikipedia.org/wiki/Logic_family and I noticed that most subclasses of circuits are linked to specific articles.

Aside from this, I would like to understand why DTL became CTDL and not CDTL.

ICE77 (talk) 01:42, 19 February 2011 (UTC)

Right now it's two lines in this article - myself, I wouldn't bother spinning it out to its own article unless there was a whole lot more about it. How notable was CTDL? If it had inductors in it, it almost certainly never made it to the monolithic integrated circuit stage. --Wtshymanski (talk) 03:24, 19 February 2011 (UTC)

If that's the case, then DCTL should not be a separate article. It should follow under RTL in a section called "DCTL". Is there any suggestion about CTDL and CDTL? Also, what would be the typical values for R₁, R₂, R₃ and R₄?

ICE77 (talk) 04:08, 19 February 2011 (UTC)

Why are you asking here? Aren't you the guy who was going to write it up? What sources do you have? Dicklyon (talk) 06:17, 19 February 2011 (UTC)

Dicklyon, I never said I was going to write the article myself. I just proposed the idea of making it.

ICE77 (talk) 03:38, 20 February 2011 (UTC)

CTDL is not distinguished by speed up capacitors or peaking inductors.

Looking at the 1401 prints, the "Complemented" moniker is a naming convention. What the 1401 calls complemented "AND" gate is what we'd call a NAND gate. See page 83, 'CTDL - TWO WAY "AND" NPN'. Except there is a twist with the logic levels. CTDL has two sets of logic level definitions: one for positive logic and the other for negative logic. There are both NPN (-6 to +6 supply, in+ out- logic) and PNP (-12 to 0 supply, in- out+ logic) flavors for gates. See page 84, 'CTDL - TWO WAY "AND" PNP'. The input logic levels are different than the output logic levels. That avoids R1 and R3 (and the whole noise immunity divider). CTDL does not "add a capacitor across R3" because R3 does not exist in the typical gate.

There's another game of complementary going on here - the designers expected to alternate NPN and PNP gates to consistently . There are level translators. See page 98. These level translators use a speed up capacitor across R3.

The basic AND gates appear to minimize time to come out of saturation with high level drive.

(The designers were also using current mode (page 96) and wired-or emitter followers (page 97). There are also other merged modules.)

Adding a peaking inductor to the load speeds things up, but that does not change that the basic logic is DTL. Peaking inductors were a common way to speed up transistors; Tektronix did it a lot in their amplifiers; I think it was called a T-coil.

CTDL has plenty of engineering insight, but it is not worthy of a separate article yet. DEC had something like FLIP modules, and it would be interesting to know if they used two different logic levels.

Glrx (talk) 17:26, 19 February 2011 (UTC)

Is it true?

"In an integrated circuit version of the gate, two diodes replace R3 to prevent any base current when one or more inputs are at low logic level. Also R4 is removed(?), and the integrated circuit runs off a single power supply voltage." Circuit dreamer (talk, contribs, email) 10:39, 17 April 2011 (UTC)

The cited web page does not support removing R4. The Computer History Museum has some interesting docs and refs that suggest the Signetics SE100 line had poor noise immunity. Perhaps the SE100 line deleted R4 and Fairchild's μL930 line used the resistor. Some old datasheets might answer the question. To me, R4 is needed to set a decent drop on the two series resistors and guarantee cutoff. Some WP:RS should be used to justify a statement about deleting R4. (See also http://homepages.nildram.co.uk/~wylie/ICs/monolith.htm for family overview and bib; http://web.archive.org/web/20050820002220/http://www.stanford.edu/group/mmdd/SiliconValley/ElectronicNews/Monolithics.text/Monolithic.rtf stating SE100 DTL had poor noise immunity; sensitive to clock waveform.) Glrx (talk) 17:19, 17 April 2011 (UTC)

We are talking about the circuit with two series connected base diodes (e.g., [1]), aren't we? The problem of this solution is the absence of a return path for discharging the base. So, I suppose that R4 is not simply removed but it is connected to ground (as it is shown in [2]). Circuit dreamer (talk, contribs, email) 20:00, 17 April 2011 (UTC)

Sorry, I see you have corrected it. Circuit dreamer (talk, contribs, email) 20:09, 17 April 2011 (UTC)

Speedup capacitor

Where are the sources for the speedup capacitor? It seems to me that with the diodes it can't possibly help in both directions; if it speeds up stored charge removal, it probably doesn't help the turnon much if at all (in the circuit shown); certainly it doesn't act like a differentiator or "force the base current" in this case. Dicklyon (talk) 15:51, 23 April 2011 (UTC)

Horowitz&Hill have said on page 908, "A small "speedup" capacitor across the base driving resistor can reduce storage time by providing a pulse of current to remove base charge at turn-off, and in addition it increases base drive current during turn-on transitions."

Diodes (as connected) do not impede charging and discharging of the capacitor. The capacitor acts as a differentiator since we apply voltage across it as an input and take the current through it as an output. I suggest to scrutinize the circuit operation during the two states. It would be well if we know the exact values of the elements (resistances and voltages). Circuit dreamer (talk, contribs, email) 17:50, 23 April 2011 (UTC)

I added two refs. Mot HS STH is silent about helping with turn on. I included its qualifying comment about low Z input drive because that can be true for the gate shown in this article for turn off. For turn on, the input diodes are off (ie, hi-Z drive), so the diode gate pull up resistor is the driving Z. I think that explains Dicklyon's reservation about helping both ways. I think H&H overstate the turn on benefit for logic, but the comment may be appropriate for switchmode drive. H&H are addressing storage time in the abstract and not specifically for DTL. Also, if the capacitor is too big, it will saturate the transistor. Glrx (talk) 19:48, 23 April 2011 (UTC)

Nothing in H&H connects this idea to DTL. Does the Moto book? Dicklyon (talk) 04:47, 24 April 2011 (UTC)

Right. While I can't provide a reference, common sense dictates there is no way of adding a capacitor to the internal circuitry of a DTL package. No description of logic circuits I have read mention the use of integrated capacitors. Speed-up capacitors have been used in discrete logic circuits. Paul Gray's book pg 303-306 and 821-841 has a good explanation of this using charge control models. For low drive switches it is used to increase the turn-on time and for saturated switches the charge on the capacitor equals the extra charge stored in the base in the on state. I don't think speedup caps to be mentioned here. Zen-in (talk) 16:27, 24 April 2011 (UTC)

H&H discuss improving the speed of saturated switches. The third stage of DTL is a saturated switch, so I believe the reference is appropriate. Similar argument for Moto HS STH. The initial ref to Baker clamp and diode methods is section on saturated switches. Much later section 7-1-4 discusses minimizing inverter switching time for RTL stage (which is similar to DTL inverter stage).

I don't understand Zen-in. Integrated circuit DTL did not use speed up capacitors; fine. Discrete logic used speedup capacitors. Why shouldn't speed up caps be mentioned? The article is not restricted to integrated circuit implementations.

Glrx (talk) 00:23, 26 April 2011 (UTC)

Every IBM DTL logic circuit implemented with discrete components used a speed up capacitor. It definitely decreased the saturation delay and also improved the turn-on speed and to some extent transition speeds. I designed most of IBM’s DTL discrete circuits from 1958 to about 1960. RTL could not use a speed up capacitor since they would have caused cross coupling of the inputs. That and the inefficiency of RTL resulted in very poor speeds. W. G. Crouse (Sorry, I came back.) — Preceding unsigned comment added by UPCMaker (talk • contribs) 21:36, 24 April 2012 (UTC)

Implementations 1401

The article in Implementations referring to the IBM 1401 claims it used DTL but avoided the R3 and R4 level shifter by using alternate NPN and PNP circuits. IBM never had DTL or any voltage mode logic circuits that required alternate level shifted circuits. All their voltage mode logic circuits provided compatible input and output levels. I believe the author is confused with IBM’s Drift Transistor Current Mode logic circuits invented by Hannon Yourke. In the DTL circuit R4 and V- were needed due to the use of Germanium Alloy Transistors which at high temperatures has very low base-emitter drops and very high collector-base leakage. I might add that after their very earliest transistor circuit family their voltage mode logic circuits used primarily PNP transistors and their DTL family achieved circuit delays near 100nsec. Yourke’s current switching family achieved 20nsec delays with Drift Transistors that cost $20 each. All these families used germanium transistors, many where hand made. The DTL circuits all used capacitors around R3 for increased speed for both saturation and cutoff delays. The extra power supplies for all circuit families were not a concern since the cost of transistors greatly out weighed the cost of power supplies. Remember this was 1955 to1960. Integrated circuits with cheap and matched silicon transistors were not quite available. Discrete silicon transistors were very expensive and unbelievably slow. W.G.Crouse is back. — Preceding unsigned comment added by UPCMaker (talk • contribs) 21:21, 24 April 2012 (UTC)

See #CTDL discussion above. You can also look at the prints, and they have nice tables for input/output levels. For example, a CTDL 3-WAY "AND" PNP EXTENDABLE INPUTS used in the 1401 has input voltages ranging from -6.24 to +6.24 and output voltage of -12.5 to 0.26; speed is 100 to 800 nS. There's no R3 or R4, so there isn't a capacitor to place around them. The logic levels are "compatible" if PNP and NPN stages alternate, but NPN stages cannot drive NPN stages because the logic levels are different. Consequently, there is also a level translator in the family. Leakage/matching is not an issue because input/base drive is bipolar: either it's push in or suck out; the inputs provide a leakage bleed path when needed. I still have some of the diodes and 034 transistors used in the 1401. IIRC, Baker said the 1956 Si cost was $200/ea. Glrx (talk) 22:55, 24 April 2012 (UTC)

I believe I worked on every IBM logic family packaged on SMS cards. I never heard of CTDL. The inductors and complementery circuits etc. sound like the Current Mode family. I tried the link for the 1401 logic but it didn't work. I would like to see the schematic for CTDL. I really think something is wrong here.UPCMaker — Preceding unsigned comment added by 75.93.213.123 (talk) 00:48, 25 April 2012 (UTC)

OK, I found the IBM CTDL schematics and I am proud to say I never worked on or knew about them. The 1401 did use Drift Current Mode logic but if they used CTDL it must have been with the idea they would save money but why they chose such a strange circuit is beyond me. It would have had all the disadvantages of DTL and Current Mode without any of the advantages. They couldn’t have just picked up our DTL directly because it required +12Volts but that would have been easy to fix. I guess you can just ignore my comments above. .UPCMaker — Preceding unsigned comment added by 75.93.213.123 (talk) 12:02, 25 April 2012 (UTC)

It sounds like the 1401 used CTDL for the slower operations and some STDL for faster ones. The CTDL schematics have both CTDL and current mode outputs. I haven't had time to digest the S- logic. CTDL has some small advantages over conventional DTL; the only disadvantage I see is the two logic level flavors (T and U). The prints have detailed graphs of switching speeds, so it is clear that IBM was serious about performance. Glrx (talk) 15:56, 25 April 2012 (UTC)

I find it hard to find anything good about CTDL even though I would like to since I was not too far away in time or space when it was created. Compared to the DTL that was known in IBM at that time it appears to be a bad choice. It saved two resistors and a capacitor all worth about 15 cents but added an inductor that cost more. I don’t know what speed they claimed but an older DTL technology handled one micro second pulses. About that time we created a new DTL family with 100 nano second delays. I am sure the CTDL design grew out of the Current Mode configuration. The alternating NPN and PNP signal levels were well justified for Current Mode because it achieved 20 nano second delays. I can’t find any justification for the same disadvantage with CTDL. They could have easily designed a conventional DTL that would have still provided what little compatibility CTDL provided. I can’t believe CTDL came out of the IBM Poughkeepsie Lab where Hannon Rourke worked. The old Circuit Tech department in the Endicott lab might have come up with the idea. B. O. Evans created our department to “assist” the old department. Being a retired IBMer with a circuit design history that coincides with this era I would hope no additional CTDL article will be seen and it might soon be forgotten. I see many comments from LSI era engineers that often don’t understand the differences between discrete transistor circuit design and LSI but CTDL does not warrant that justification. UPCMaker — Preceding unsigned comment added by 75.93.213.123 (talk) 19:10, 25 April 2012 (UTC)