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Intel Hub Architecture

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This is an old revision of this page, as edited by Payam81 (talk | contribs) at 05:22, 31 March 2006 (Add IHA2). The present address (URL) is a permanent link to this revision, which may differ significantly from the current revision.

Intel's architecture for the 8xx family of chipsets, starting with the 820. It uses a memory controller hub (MCH) that is connected to an I/O controller hub (ICH) via a 266 MB/sec bus. The MCH chip supports memory and AGP, while the ICH chip provides connectivity for PCI, USB, sound, IDE hard disks and LAN.

Because of the high-speed channel between the sections, the Intel Hub Architecture (IHA) is much faster than the earlier Northbridge/Southbridge design, which hooked all low-speed ports to the PCI bus. The IHA also optimizes data transfer based on data type.

Next Generation

Intel Hub Architecture 2.0 is currently employed in to Intel's line of E7xxx server chipsets.

First Intel chipset to use IHA

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