Open Verification Methodology

Hello_world from deaccella uvm. I let the poorness of uvm speak for itself:

module hello_world;

import uvm_pkg::*;

`include "uvm_macros.svh"

`include "packet.sv"

`include "producer.sv"

`include "consumer.sv"

`include "top.sv"

top mytop;

initial begin

$timeformat(-9,0," ns",5);

uvm_default_table_printer.knobs.name_width=20;

uvm_default_table_printer.knobs.type_width=50;

uvm_default_table_printer.knobs.size_width=10;

uvm_default_table_printer.knobs.value_width=14;

set_config_int("top.producer1","num_packets",2);

set_config_int("top.producer2","num_packets",4);

set_config_int("*","recording_detail",UVM_LOW);

//uvm_default_printer = uvm_default_tree_printer;

uvm_default_printer.knobs.reference=0;

mytop = new("top");

uvm_default_table_printer.knobs.type_width=20;

run_test();

end

endmodule

class top extends uvm_component;

producer #(packet) p1;

producer #(packet) p2;

uvm_tlm_fifo #(packet) f;

consumer #(packet) c;

`uvm_component_utils(top)

function new (string name, uvm_component parent=null);

super.new(name,parent);

p1 = new("producer1", this);

p2 = new("producer2", this);

f = new("fifo", this);

c = new("consumer", this);

p1.out.connect( c.in );

p2.out.connect( f.blocking_put_export );

c.out.connect( f.get_export );

endfunction

task run_phase(uvm_phase phase);

phase.raise_objection(this);

uvm_top.print_topology();

#1us;

phase.drop_objection(this);

endtask

endclass

class consumer #(type T=packet) extends uvm_component;

uvm_blocking_put_imp #(T,consumer #(T)) in;

uvm_get_port #(T) out;

function new(string name, uvm_component parent=null);

super.new(name,parent);

in = new ("in", this);

out= new ("out",this, 0);

endfunction

protected int count = 0;

local semaphore lock = new(1);

`uvm_component_utils_begin(consumer #(T))

`uvm_field_int(count,UVM_ALL_ON + UVM_READONLY + UVM_DEC)

`uvm_component_utils_end

task run_phase(uvm_phase phase);

T p;

while(out.size()) begin

out.get(p);

put(p);

end

endtask

task put (T p);

lock.get();

count++;

// void'(accept_tr(p));

accept_tr(p);

#10;

void'(begin_tr(p));

#30;

end_tr(p);

`uvm_info("consumer", $sformatf("Received %0s local_count=%0d",p.get_name(),count), UVM_MEDIUM)

if(uvm_report_enabled(UVM_HIGH,UVM_INFO,""))

p.print();

lock.put();

endtask

endclass

class packet extends uvm_transaction

`ifndef NO_RAND

rand

`endif

int addr;

`uvm_object_utils_begin(packet)

`uvm_field_int(addr, UVM_ALL_ON)

`uvm_object_utils_end

constraint c { addr >= 0 && addr < 'h100; }

endclass

class producer #(type T=packet) extends uvm_component;

uvm_blocking_put_port #(T) out;

function new(string name, uvm_component parent=null);

super.new(name,parent);

out = new("out",this);

void'(get_config_int("num_packets", this.num_packets));

endfunction

protected T proto = new;

protected int num_packets = 1;

protected int count = 0;

`uvm_component_utils_begin(producer #(T))

`uvm_field_object(proto, UVM_ALL_ON + UVM_REFERENCE)

`uvm_field_int(num_packets, UVM_ALL_ON + UVM_DEC)

`uvm_field_int(count, UVM_ALL_ON + UVM_DEC + UVM_READONLY)

`uvm_component_utils_end

task run_phase(uvm_phase phase);

T p;

string image, num;

`uvm_info("producer", "Starting.", UVM_MEDIUM)

for (count =0; count < num_packets; count++) begin

$cast(p, proto.clone());

num.itoa(count);

p.set_name({get_name(),"-",num});

p.set_initiator(this);

if (uvm_verbosity'(recording_detail)!=UVM_NONE)

p.enable_recording("packet_stream");

void'(p.randomize());

`uvm_info("producer", $sformatf("Sending %s",p.get_name()), UVM_MEDIUM)

if(uvm_report_enabled(UVM_HIGH,UVM_INFO,""))

p.print();

out.put(p);

#10;

end

`uvm_info("producer", "Exiting.", UVM_MEDIUM);

endtask

endclass

Final comments

One only needs to look at the hello world example from deaccella uvm to realized how utter stupid and poorly misconceived uvm really is.

The whole point of object oriented is to make the code simpler, more maintainable and easier to read by abstacting away the complexity of the problem. OVM is the complete opposite, its a poorly conceived, messy, misnamed, with trash and dirt thrown everywhere. it may work in the end, but it take 4 times longer to use, maintain, and to find enough people that can hide and pretend that they don't really know how to use it without copying somebody else's work.

Even the hello world ovm from deaccella sucks. Who can honestly with a straight face say that ovm is good after looking at the hello world example. Side-by-side, truthful, and honest comparion... non-ovm wins everytime.. the same task is even easier to accomplish with only system verilog minus shitty ovm classes.

There are many idiot verification managers and do-nothing verification leads that actually think that uvm hello_word is good code because they have no idea how to write real code. That only proves how incompetant and desevering they are to be fired and replaced with experienced ASIC Designers that know how to design the real logic. Managers that pretend that OVM is important should be demoded and fired to let somebody more qualified make these decisions on how to verify the design.

==SystemVerilog

The Open Verification Methodology (OVM) is a documented methodology with a supporting building-block library for the verification of semiconductor chip designs. The initial version, OVM 1.0, was released in January, 2008, and regular updates have expanded its functionality. The latest version is OVM 2.1.1, released in April, 2010. The current release and all previous releases are available, under the Apache License, on the OVM World site.

The reuse concepts within the OVM were derived mainly from the URM (Universal Reuse Methodology) which was, to a large part, based on the eRM (e Reuse Methodology) for the e Verification Language developed by Verisity Design in 2001. The OVM also brings in concepts from the AVM (Advanced Verification Methodology (AVM). The UVM class library brings much automation to the SystemVerilog language such as sequences and data automation features (packing, copy, compare) etc. The UVM also has recommendations for code packaging and naming conventions.

The OVM has won recognition from Electronic Design Magazine and a DesignVision award from the International Engineering Consortium.

The OVM was co-developed by Mentor Graphics and Cadence Design Systems, and they continue to guide its evolution in concert with the nine user companies of the OVM Advisory Group. The OVM is publicly supported by more than 60 partner companies offering tools, training, and services.

The OVM was standardized within Accellera, which voted to make it the basis for the Universal Verification Methodology (UVM). Accellera released version UVM 1.0 EA on May 17, 2010 ..