Bit-serial architecture
In digital logic applications, bit-serial architectures are contrasted to bit-parallel, where a data word tends to be a one-to-one function of the system clock signal. A bit-serial architecture processes a data word as a function of the system clock signal multiplied by the length of the data word. Hence, only one bit of data is processed in a given component at a given point in time.
References
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External links
- Application of FPGA technology to accelerate the finite-difference time-domain (FDTD) method
- BIT-Serial FIR filters with CSD Coefficients for FPGAs