Load Program Status Word instruction
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In the System/360 line of IBM mainframe computers up to contemporary zSeries, the Load Program Status Word instruction (LPSW) is a privileged instruction used to restore the program status, including the mode and key, and the next sequential instruction address after the interruption. The interruption could be any of a set of interruptions (SVC, I/O, timer/external, etcetera). LPSW could be considered the complement of any interruption, in general, and an SVC interruption, in particular.
In those cases where the SVC is Type 1 (or, in MVS, Type 6), the return is expected to be immediate, and the LPSW is generally done from the SVCOPSW (Supervisor Call Old PSW, a specific location in main storage which is defined by the architecture).
In those cases where the SVC is Types 2, 3 or 4, the return is expected to be delayed, and the LPSW is generally done from the PSW which was temporarily stored in the PRB (i.e., moved to the PRB from the SVCOPSW).
In MVS/370 and later instances of the OS, a mechanism exists for preempting parts of these processes, for purposes of efficiency and system integrity, but the actual return to the interrupted program is processed logically as is herein described.