System bus model
 | It has been suggested that this article be merged into Von Neumann architecture. (Discuss) Proposed since October 2010. |
| It has been suggested that this article be merged into System bus. (Discuss) Proposed since May 2011. |
The system bus model is a streamlined version of the von Neumann model of computer architecture.[1] Its main feature is that it interconnects the processor, memory, and I/O subsystems by a single bus, divided in 3 components: data bus, address bus, control bus.[2]
Communications
The system bus models divides the computer into three individual subunits which are the CPU, memory and input/output. The system bus model deviates from the von Neumann model by combining the arithmetic logic unit (ALU) and the central processing unit (CPU) into a single unit.[2]
The system bus is composed of the data bus, address bus, and control bus.[2]
The data bus is used for transfer of data between subunits while the address bus is used to transmit information to determine where the data should be sent.[2]
The control bus is used to provide information as to how data is being sent.[2]
References
- ^ Linda Null; Julia Lobur (2006). The essentials of computer organization and architecture (2 ed.). Jones & Bartlett Learning. ISBN 9780763737696.
- ^ a b c d e Murdocca, Miles J. (2000). Principles of Computer Architecture. Prentice-Hall. p. 5. ISBN 0-201-43664-7.
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