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MESIF protocol

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The MESIF protocol is a cache coherency and memory coherence protocol developed by Intel for cache coherent non-uniform memory architectures[1]. The protocol consists of five states, Modified (M), Exclusive (E), Shared (S), Invalid (I) and Forward (F).

The M, E, S and I states are the same as in the MESI protocol. The F state is a specialized form of the S state, and indicates that a cache should act as a designated responder for any requests for the given line. The protocol ensures that, if any cache holds a line in the S state, exactly one (other) cache holds it in the F state.

In a system of caches employing the MESI protocol, a cache line request that is received by multiple caches holding a line in the S state will receive multiple responses. In a system of caches employing the MESIF protocol, a cache line request will be responded to only by the cache holding the line in the F state[2].

For any given pair of caches, the permitted states of a given cache line are as follows:

 M   E   S   I   F 
 M  Red XN Red XN Red XN Green tickY Red XN
 E  Red XN Red XN Red XN Green tickY Red XN
 S  Red XN Red XN Green tickY Green tickY Green tickY
 I  Green tickY Green tickY Green tickY Green tickY Green tickY
 F  Red XN Red XN Green tickY Green tickY Red XN

References

  1. ^ http://www.realworldtech.com/page.cfm?ArticleID=RWT082807020032&p=5
  2. ^ US Patent 6922756, http://www.google.com/patents/about?id=MzYVAAAAEBAJ&dq=6922756
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