IBM System/360 architecture
IBM System/360 architecture
While this is currently a stand-alone article, the intent is to eventually merge it into IBM System/360
<!- ==Architecture== -> The architecture of the System/360 is independent of its implimentation on any specific processor, and includes the following elements.
Memory
Memory (storage) in the S/360 is addressed in terms of 8-bit bytes. Various instructions operate on larger units called half word (2 bytes), word (4 bytes), double word (8 bytes), quad word (16 bytes) and 2048 byte storage block. Within a half word, word, double word or quad word, low numbered bytes are more significant than high numbered bytes. Many architected uses of these units require that they be aligned on the corresponding boundaries.
Addressing
The S/360 uses truncated addressing. That means that instructions do not contain complete addresses, but rather specify base address and offsets past those base addresses. In the case of the S/360 the base address is contained in one of 15 general registers. In some instructions, e.g., shifts, the same computations are performed for 32-bit quantities that are not addresses.
Instruction formats
Instructions in the S/360 are one, two or three halfwords, with the opcode in byte 0, and have one of the following formats:
- RR. Generally byte 1 specifies two 4-bit register numbers, but in some cases, e.g., SVC, byte 1 is a single 8-bit immediate field.
- RS. Byte 1 specifies two register numbers; bytes 2-3 specify a base and displacement.
- RX. Byte 1 bits 0-3 specifies either a register number or a modifier; byte 1 bits 4-7 specifies the number of the general register to be used as an index; bytes 2-3 specify a base and displacement.
- SI. Byte 1 specifies an immediate field; bytes 2-3 specify a base and displacement.
- SS. Byte 1 specifies two 4-bit length fields or one 8-bit length field; bytes 2-3 and 4-5 each specify a base and displacement. The encoding of the length fileds is length-1.
Program Status Word (PSW)
The Program Status Word (PSW) Contains a vaiety of controls for the currently operating program
| bits | contents | Explanation | |
|---|---|---|---|
| 0-7 | SM | System Mask | See below; 1 if enabled |
| 0 | Channel 0 | ||
| 1 | Channel 1 | ||
| 2 | Channel 2 | ||
| 3 | Channel 3 | ||
| 4 | Channel 4 | ||
| 5 | Channel 5 | ||
| 6 | Channel 6 | ||
| 7 | Timer Interrupt key External signal |
||
| 8-11 | Key | CPU protection key to compare against storage protection keys | |
| 12-15 | AMWP | See below; 1 if enabled | |
| 12 | A | ASCII | ASCII mode for packed decimal instructions Never used by IBM software. |
| 13 | M | Machine check | Allow machine-check interrupts. |
| 14 | W | Wait State | Processor is waiting for interrupts. |
| 15 | P | Problem state | |
| 16-31 | IC | Interruption Code | Interpretation depends on type of interrupt. This field is not used in the PSW itself, but a value is inserted when the PSW is stored as part of processing an interrupt. |
| 32-33 | ILC | Instruction Length Code | Interpreted as 2-bit number: length in halfwords or 0 if unavailable. |
| 34-35 | CC | Condition Code | See individual instructions for encoding |
| 36-39 | PM | Program Mask | See below; 1 if enabled |
| 36 | Fixed-point overflow | ||
| 37 | Decimal overflow | ||
| 38 | Exponent underflow | ||
| 39 | Significance | ||
| 40-63 | IA | Instruction Address |