Bus functional model

Bus Functional Model or BFM is a non-synthesizable software model of an integrated circuit component. This software model can be used to simulate the behavior of a hardware system before building and testing the actual hardware. BFM's are usually defined as tasks in HDL s which applies stimulus to the design under test/verification via complex waveforms and protocols. A BFM is typically written in an HDL language such as verilog, VHDL,SystemC or SystemVerilog.

On one side, it drives and samples low-level signals according to pre-defined protocol. On the other side,tasks are available to initiate a transaction with specified data values.BFMs are often used as reusable building blocks to create simulation testbenches, where the signal ports on a design under test are connected to the appropriate BFMs in the testbench for the purpose of simulation.

Transaction Verification Models

BFMs are sometimes referred to as TVMs or Transaction Verification Models. This is to emphasize that bus operations of the model have been bundled into atomic bus transactions to make it easier to issue and view bus transactions. Viewing of bus transactions of TVMs is similar to viewing the output of a protocol analyzer or bus sniffer.

External References

• Manual and Automatic VHDL/Verilog Test Bench Coding Techniques