Interface logic model

Interface Logic Model (ILM) is a technique to model blocks in hierarchal VLSI implementation flow.

The advantage of ILM is that entire path ( clock to clock path) is visible at top level for interface nets unlike traditional block based hierarchal implementation flow. That gives better accuracy in analysis for interface nets at negligible additional memory and runtime overhead.

References

• [http://www.emba.uvm.edu/~jswift/uvm_class/notes/phys_syn.pdf Introduction to Physical

Compiler and ILM Flow]