Processor supplementary capability

A processor supplementary capability is a feature that has been added to an existing central processing unit design after the initial introduction of that design to the marketplace.

A supplementary capability increases the usefulness of the processor design, allowing it to compete more favorably with competitors and giving consumers a reason to upgrade, while retaining backwards compatibility with the original design.

However, the feature will not be found on all processors within that family. A programmer who wishes to use a supplementary feature of a CPU is faced with a couple of choices. The programmer may design the software so that it mandatorily uses that feature and therefore can only be run on the more recent processors that have that feature; or the software may determine whether the processor it is running on has a particular feature before trying to use that feature, and fall back to a (presumably slower or otherwise less desirable) alternative technique or else run with reduced functionality. In other cases, an operating system may mimic the new features for older processors, though often with reduced performance. By using a lowest common denominator strategy (avoiding utilization of processor supplementary capabilities), programs can be kept portable across all machines of the same architecture.

Some popular processor architectures (such as x86, 68000 and MIPS architecture) have seen many new capabilities introduced over several generations of design. Some of these capabilities have then seen widespread adoption by programmers, spurring consumer upgrades and making the previous generations of processors obsolete.

Extended Capability Flags

The following processor supplementary capabilities features are not available on all computers designated as IBM Compatible, and may cause compatibility issues, if utilized on certain machines:

VME 	Virtual 8086 Mode Enhancement 	
DE 	Debugging Extensions 	
PSE 	Page Size Extensions 	
TSC 	Time Stamp Counter 	
MSR 	RDMSR and WRMSR Support 	
PAE 	Physical Address Extensions 	
MCE 	Machine Check Exception 	
CXS 	CMPXCHG8B Instruction 	
APIC 	APIC on Chip 	
MTRR 	Memory Type Range Register 	Not available on all Pentium compatible processors
PGE 	PTE Global Bit 	
MCA 	Machine Check Architecure 	
CMOV 	Conditional Move and Compare Instructions

Supplementary Capabilities Not Represented By Flags

Processor Supplementary Instructions

Processor Supplementary Instructions are instructions that have been implemented on certain processors within a family, but are not present on all processors within a particular family.

IA-32

The following instructions are considered to be processor supplementary instructions on IA-32 architecture. These instructions were added to later production processors, and are not part of the original IA-32 instruction set. Programs containing these instructions may not operate correctly on all machines in the IA-32 family:

Other architectures

Floating Point Unit Capability

The FPU maths co-processing capability is available on all x86 processors since the 80486DX series.