Functional verification

Functional verification, in electronic design automation, is the task of verifying that the logic design actually does what is intended. This is a very difficult task, equivalent to program verification, and takes the majority of time and effort in almost all large electronic system design.

Since the problem is difficult, it is attacked by many methods. None of them are perfect, but all of them are helpful.

• Logic simulation simulates the logic before it is built.
• Simulation acceleration applies special purpose hardware to the logic simulation problem.
• Emulation builds a version of system using programmable logic. This is expensive, and still much slower than the real hardware, but orders of magnitude faster than simulation. It can be used, for example, to boot the operating system on a hypothetical processor.
• Formal verification attempts to show mathematically that certain requirements (also expressed formally) are met, or that certain undesired behaviors (such as deadlock) cannot occur.
• Heuristics such as code coverage or HDL-specific versions of lint are commonly used to find common problems.