MESIF protocol
The MESIF protocol is a cache coherency and memory coherence protocol developed by Intel for cache coherent non-uniform memory architectures[1]. The protocol consists of five states, Modified (M), Exclusive (E), Shared (S), Invalid (I) and Forward (F). The M, E, S and I states are the same as in the MESI protocol. The F state indicates that a cache should act as a designated responder for any requests for the given line. In a system of caches employing the MESI protocol, a cache line request that is received by multiple caches holding a line in the S state will receive multiple responses. In a system of caches employing the MESIF protocol, a cache line request will be responded to only by the cache holding the line in the F state[2].
For any given pair of caches, the permitted states of a given cache line are as follows:
| M | E | S | I | F | |
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| F | |
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