Template:Infobox CPU architecture/doc

This template is for CPU architectures.

Usage

{{Infobox CPU architecture
| name       = 
| designer   = 
| bits       = 
| introduced = 
| version    = 
| design     = 
| type       = 
| encoding   = 
| branching  = 
| endianness = 
| extensions = 
| open       = 
| registers  = 
| gpr          =
| fpr           =
}}

Description

{{Infobox CPU architecture
| name       = Name of architecture, e.g. x86, SPARC, PowerPC, MIPS, ARM
| designer   = Designer of the architecture
| bits       = Width of accumulator/general registers/stack top, e.g. 32-bit, 64-bit
| introduced = Year introduced
| version    = Version/revision of architecture/ISA
| design     = Design strategy, e.g. RISC, CISC
| type       = Type of architecture, e.g. Register-Register, Register-Memory, Memory-Memory
| encoding   = Instruction set encoding, e.g. Fixed or Variable
| branching  = Branching evaluation, e.g. Condition register, Condition code, Compare and branch
| endianness = Byte ordering, i.e. Little, Big, Bi
| extensions = ISA extensions, i.e. MMX, SSE, AltiVec, etc
| open       = Is the architecture open or not? (as in free or proprietary)
| registers  = Number and size of processor registers 
| gpr          = Number and size of general-purpose registers
| fpr           = Number and size of floating-point registers
}}

All fields are optional.

Example

SPARC

Designer	Sun Microsystems
Bits	64-bit (32 → 64)
Introduced	1985
Version	V9
Design	RISC
Type	Register-Register
Encoding	Fixed
Branching	Condition code
Endianness	Bi (Big → Bi)
Extensions	VIS 1.0, 2.0, 3.0
Open	Yes
Registers
32

{{Infobox CPU architecture
| name       = SPARC
| designer   = [[Sun Microsystems]]
| bits       = 64-bit (32 → 64) 
| introduced = 1985
| version    = V9
| design     = RISC
| type       = Register-Register
| encoding   = Fixed
| branching  = Condition code
| endianness = Bi (Big → Bi)
| extensions = [[Visual Instruction Set|VIS]] 1.0, 2.0, 3.0
| open       = Yes
| registers  = 32
}}

Parameters

All parameters are optional.

name

Name of architecture, e.g. x86, SPARC, PowerPC, MIPS, ARM

designer

Designer of the architecture

bits

Width of accumulator/general registers/stack top, e.g. 32-bit, 64-bit

introduced

Year introduced

version

Version/revision of architecture/ISA

design

Design strategy, e.g. RISC, CISC

type

Type of architecture, e.g. Register-Register, Register-Memory, Memory-Memory

encoding

Instruction set encoding, e.g. Fixed or Variable

branching

Branching evaluation, e.g. Condition register, Condition code, Compare and branch

endianness

Byte ordering, i.e. Little, Big, Bi

extensions

ISA extensions, i.e. MMX, SSE, AltiVec, etc

open

Is the architecture open or not? (as in free or proprietary)

registers

Number and size of process registers, general purpose registers, floating-point registers, etc

gpr

Amount and width of general-purpose registers

fpr

Amount and width of floating-point registers

See also

• Template:Infobox CPU(edit talk links history) for central processing units
• Template:Infobox Computer Hardware Bus(edit talk links history) for computer buses