Talk:Instruction-level parallelism

Hi:

The 1st sentence of the last paragraph of instruction level parallelism says "As of 2004, the computer industry has hit a roadblock in getting further performance gains from ILP". I wondering what roadblock refers to. Does it refer to software techniques or hardware techniques? From which papers/reports/experiences/perspectives, the author made this assumption? I am a student and curious about it.

Thanks very much!

John

The roadblock that I was referring to was the difference in operating frequencies between the CPU and main memory. CPUs are now running in multiple Gigahertz (1 cycle << 1 nanosecond), while the access of times of DRAMS are still in the range of ~50 nanoseconds. The result is that any memory reference that misses within all of the on-chip caches will force the CPU to encur a penalty of hundreds of cycles. None of the techniques that exploit ILP can overcome this very large discrepancy. That's why a PC with a 4Ghz CPU is only marginally faster then one with a 3Ghz CPU. Dyl 23:45, 28 November 2005 (UTC)