EnCore Processor
Appearance

The EnCore microprocessor family is a configurable and extendable implementation of a compact 32-bit RISC instruction-set architecture - developed by the PASTA Research Group at the University of Edinburgh School of Informatics. The following are key features of the EnCore microprocessor family:
- 5 stage pipeline
- highest operating frequency in its class
- lowest possible dynamic energy consumption - 99% of flip-flops automatically clock-gated using typical synthesis tools
- most non-memory operations achieving single-cycle latency, and no more than one load-delay slot
- easy configurability of cache architectures
- compact baseline ISA, including freely-mixed 16-bit and 32-bit encodings for maximum code density
- no overhead for switching between 16- and 32-bit encodings
All of the EnCore test chips are named after hills in Edinburgh; Calton, being the smallest, is the first of these.

The first silicon implementation of the EnCore processor is a test-chip code-named Calton, fabricated in a generic 130nm CMOS process.
- 130nm implementation of EnCore processor in baseline configuration extended with barrel shifter, multiplier, and a full set of 32 general purpose registers.
- Contains bus interface and system control functions, in addition to the processor.
- Implemented with 8KB direct-mapped instruction- and data-cache.
- Complete system-on-chip occupies 1 mm2 of silicon at 75% utilization.
- Chip-level power consumption is 25 mW at 250 MHz.
- First silicon samples operate above a frequency of 375 MHz at typical voltage and temperature.
This article has not been added to any content categories. Please help out by adding categories to it so that it can be listed with similar articles. (June 2009) |