Template:Infobox CPU architecture/doc

SPARC
Designer	Sun Microsystems
Introduced	1985
Version	V9
Design	RISC
Type	Register-Register
Encoding	Fixed
Branching	Condition code
Endianness	Bi (Big → Bi)
Extensions	VIS 1.0, 2.0, 3.0
Open	Yes
Registers
	32

This is a documentation subpage for Template:Infobox CPU architecture.
It may contain usage information, categories and other content that is not part of the original template page.

This template is for CPU architectures.

Usage

{{Infobox CPU architecture
| name       = Name of architecture, e.g. x86, SPARC, PowerPC, MIPS, ARM
| designer   = Designer of the architecture
| bus        = Width of bus, e.g. 32-bit, 64-bit
| introduced = Year introduced
| version    = Version/revision of architecture/ISA
| design     = Design strategy, e.g. RISC, CISC
| type       = Type of architecture, e.g. Register-Register, Register-Memory, Memory-Memory
| encoding   = Instruction set encoding, e.g. Fixed or Variable
| branching  = Branching evaluation, e.g. Condition register, Condition code, Compare and branch
| endianness = Byte ordering, i.e. Little, Big, Bi
| extensions = ISA extensions, i.e. MMX, SSE, AltiVec, etc
| open       = Is the architecture open or not? (as in free or proprietary)
| registers  = Number and size of process registers, general purpose registers, floating-point registers, etc 
}}

All fields are optional.

Example

{{Infobox CPU architecture
| name       = SPARC
| designer   = [[Sun Microsystems]]
| bus        = 64-bit (32 → 64) 
| introduced = 1985
| version    = V9
| design     = RISC
| type       = Register-Register
| encoding   = Fixed
| branching  = Condition code
| endianness = Bi (Big → Bi)
| extensions = [[Visual Instruction Set|VIS]] 1.0, 2.0, 3.0
| open       = Yes
| registers  = 32
}}

Parameters

All parameters are optional.

name: Name of architecture, e.g. x86, SPARC, PowerPC, MIPS, ARM
designer: Designer of the architecture
bus: Width of bus, e.g. 32-bit, 64-bit
introduced: Year introduced
version: Version/revision of architecture/ISA
design: Design strategy, e.g. RISC, CISC
type: Type of architecture, e.g. Register-Register, Register-Memory, Memory-Memory
encoding: Instruction set encoding, e.g. Fixed or Variable
branching: Branching evaluation, e.g. Condition register, Condition code, Compare and branch
endianness: Byte ordering, i.e. Little, Big, Bi
extensions: ISA extensions, i.e. MMX, SSE, AltiVec, etc
open: Is the architecture open or not? (as in free or proprietary)
registers: Number and size of process registers, general purpose registers, floating-point registers, etc