Processor supplementary capability

Processor Supplementary Capabilities are features that have been introduced ad-hoc to certain models of computer central processing units that are not present on all processors within a particular architecture or family.

Programs that utilize processor supplementary capabilities may not be compatible with all processors within a range.

Extended Capability Flags

The following processor supplementary capabilities features are not available on all computers designated as IBM Compatible, and may cause compatibility issues, if utilized on certain machines:

VME 	Virtual 8086 Mode Enhancement 	
DE 	Debugging Extensions 	
PSE 	Page Size Extensions 	
TSC 	Time Stamp Counter 	
MSR 	RDMSR and WRMSR Support 	
PAE 	Physical Address Extensions 	
MCE 	Machine Check Exception 	
CXS 	CMPXCHG8B Instruction 	
APIC 	APIC on Chip 	
MTRR 	Memory Type Range Register 	Not available on all Pentium compatible processors
PGE 	PTE Global Bit 	
MCA 	Machine Check Architecure 	
CMOV 	Conditional Move and Compare Instructions

Supplementary Capabilities Not Represented By Flags

Processor Supplementary Instructions

Processor Supplementary Instructions are instructions that have been implemented on certain processors within a family, but are not present on all processors within a particular family.

IA-32

The following instructions are considered to be processor supplementary instructions on IA-32 architecture. These instructions were added to later production processors, and are not part of the original IA-32 instruction set. Programs containing these instructions may not operate correctly on all machines in the IA-32 family:

Other architectures

Floating Point Unit Capability

The FPU maths co-processing capability is available on all processors since the 80486DX series.

Problems caused implementation of Processor Supplementary Capabilities and Instructions

One of the problems caused by utilization of processor supplementary capabilities from within a program, is that the program may not run, or may run differently on a machine that is the same architecture, but with different processor supplementary capabilities.

This leads to scenarios where Machine B is compatible with Machine A, but Machine A is not compatible with Machine B. Further scenarios are that Machine C and Machine B are both compatible with Machine A, but not compatible with each other.

Lowest Common Denominator Strategy

By using a lowest common denominator strategy (avoiding utilization of processor supplementary instructions and processor supplementary capabilities), programs can be kept portable across all machines of the same architecture.