XOP instruction set
The XOP instruction set, announced by AMD on May 1, 2009, is an extension to the 128-bit SSE core instructions in the X86 and AMD64 instruction set for the Bulldozer processor core, due to begin production in 2011[1].
XOP is a revision of the SSE5 instruction set announced on August 30, 2007. This revision makes the binary coding of the proposed new instructions more compatible with Intels AVX instruction extensions, while the functionality of the instructions is unchanged.
The XOP instructions include:
- Integer vector multiply-accumulate instructions
- Integer vector horizontal addition
- Integer vector compare
- Integer vector shift and rotate instructions
- Vector byte permutation
- Vector conditional move instructions
- Floating point fraction extraction
The XOP instruction set is supplemented by the FMA4 (floating point vector multiply-accumulate) and CVT16 (Half precision floating point conversion) instruction sets, which were also included in SSE5.