Intelligent verification
Intelligent Verification, also referred to as intelligent testbench, is a form of functional verification used to verify that an electronic hardware design conforms to specification before device fabrication. Intelligent verification uses information derived from the design and existing test description to automatically update the test description to target design functionality not verified, or “covered” by the existing tests.
Intelligent verification software has this key property: given the same test environment, the software will automatically change the tests to improve functional design coverage in response to changes in the design. Other properties of intelligent verification may include:
- Providing direction as to why certain coverage points were not detected.
- Automatically tracking paths through design structure to coverage points, to create new tests.
- Ensuring that various aspects of the design are only verified once in the same test sets.
“Intelligent Verification” uses existing logic simulation testbenches, and automatically targets and maximizes the following types of design coverage:
- Code coverage
- Branch coverage
- Expression coverage
- Functional coverage
- Assertion coverage
History
Achieving confidence that a design is functionally correct continues to become more difficult. To counter these problems, in the late 1980’s fast logic simulators and specialized hardware description languages such as Verilog and VHDL became popular. In the 1990’s, constrained random simulation methodologies emerged using hardware verification languages such as Vera [1] and ‘e’, as well as SystemVerilog (in 2002), to further improve verification quality and time.
Intelligent verification approaches supplement constrained random simulation methodologies, which bases test generation on external input rather than design structure.[2] Intelligent verification is intended to automatically utilize design knowledge during simulation, which has become increasingly important over the last decade due to increased design size and complexity, and a separation between the engineering team that created a design and the team verifying its correct operation.[1]
There has been substantial research into the intelligent verification area, and commercial tools that leverage this technique are just beginning to emerge.
See also
Vendors offering Intelligent Verification
Footnotes
- ^ a b "Leveraging Design Insight for Intelligent Verification Methodologies", Embedded, June 2008.
- ^ "Constrained random test struggles to live up to promises" SCDSource, March 2008.
References
- "Mentor offers 'intelligent' testbench generation tool" SDCSource, Feb 18, 2008.
- "Nusym focuses on intelligent verification" EETimes, May 2008.
- "Lifting the Fog on Intelligent Verification" SCDSource, May 2008.