Talk:Depletion-load NMOS logic

Sources (Aug. 2008)

Hello

I have looked-up for references according to HMOS. All I've found is that it means the technologic level (see de.WP article) but no reference with the circuit topology cu --Biezl (talk) 17:36, 25 August 2008 (UTC)[reply]

Good point. I really should've been better about that. Unfortunately the single de wp ref is for a late-generation version and hence not a good into. The topology involved is implied by the term "depletion load": there is a load device (ie pseudo-NMOS) is a depletion-mode transistor. Google for depletion load for more info. Potatoswatter (talk) 20:42, 25 August 2008 (UTC)[reply]

Pseudo-NMOS refers to gates that, within a CMOS design, uses a pMOS transistor with grounded gate as load. HenkeB (talk) 23:07, 12 January 2009 (UTC)[reply]

Now I've visted a technical library and looked-up some books. I've found non who mentions HMOS, but always NMOS-logic with depletion load. One was written in english. Maybe you can find this in your library. Something I've recognized is that Intel_8080 had NMOS mit enhancement load and 6 µm size the orginal Intel_8086 was build using NMOS with depletion load and 3 µm size (compare HMOS I). So intel started with HMOS as depletion load was introduced.

The first 8086 version was actually implemented in plain depletion-load nMOS, before switching to HMOS. HMOS was originally developed and intended for fast SRAMs but employed for other products, such as microprocessors, as they became more important. HenkeB (talk) 23:07, 12 January 2009 (UTC)[reply]

Finally I can't definitly say what's correct. I think the article can be left as it is and hopefully someone finds more definite sources in future.

VLSI Design Techniques for Analog and Digital Circuits: Geiger, Allen, Strader ISBN:007100728-8 page 535

BTW: To clearify what we're talking about look at Image:Nmos depletion and.svg which shows circuit diagram. (actually NAND)

--Biezl (talk) 16:20, 16 September 2008 (UTC)[reply]

HMOS was used more as a marketing term than in technical journals, but lives on in history. Therefore I think it deserves an article. Neither term is uniquely "correct." Thanks for the image! As depletion mode transistors are no longer used in logic, it would be nice to clarify the symbols though. Potatoswatter (talk) 17:35, 16 September 2008 (UTC)[reply]

high performance nmos?

Hi! I don't mean to be rude or aggressive here, but, what (significant) stylistic errors did I introduce? And, shouldn't pure facts have somewhat higher priority than such details? Also, I was planning to add information later (and let others do the same), I didn't have the time to fix everything at once.

You misspelled "depletion," bolded words for no reason, etc.

That's a shame! HenkeB (talk) 03:58, 13 January 2009 (UTC)[reply]

What "pure facts" did you add?

See below, please. HenkeB (talk) 03:58, 13 January 2009 (UTC)[reply]

Only very early nMOS designs, such as the 8080 (the 8008 used pMOS), used enhancement-load, demanding +/-5V and 12V, which depletion-load circuits does not. It is also fairly clearly stated/implied in datasheets (for 8086 etc) as well as in other documents (for instance, by 8086 designer Stephen Morse et al) that Intel's HMOS, HMOS-II and HMOS-III processes are (geometrically scaled) variants of depletion-load nMOS. I don't know exactly what it is that Motorola calls HMOS, but probably something similar.

OK, so we agree that depletion-NMOS and HMOS are the same thing.

No, not really, Intel's HMOS is a special case of depletion-mode NMOS, they call it scaled NMOS (see Intel microprocessors - 8008 to 8086 by Stephen Morse et al, for instance). Motorola seems to call it scaled or high-density NMOS depending on the particular 6800/6809 data sheet. HenkeB (talk) 03:59, 13 January 2009 (UTC)[reply]

It's therefore quite odd (to say the least) to try to contrast HMOS against nMOS like the article now does (again). Not to be harsh, but it is nothing but a plain confusion with the distinction between depletion-load and enhacement-load nMOS. I belive depletion-load nMOS is a by far more important encyclopedia entry than is HMOS, as the term is technically well defined and actually mean something in itself (also, why call depletion load nMOS "tuned" transistors etc?). HenkeB (talk) 20:52, 12 January 2009 (UTC)[reply]

NMOS refers excusively to enhancement-load. HMOS refers excusively to depletion-load. As for which term is more widespread, see Google. Any more questions? Potatoswatter (talk) 02:08, 13 January 2009 (UTC)[reply]

Yes I have more questions: What did you get that from (superficial google searches?), and what do you then like to call the processes or technologies used to implement the 6800, 6502, 6510, 6809, Z80, etc (as well as early 8085 and 8086 chips)? These were all marketed as NMOS or N-channel MOS while at the same time using depletion-load (and silicon gate) technology, according to data sheets. Do you say we should retroactively rename these to "HMOS", because there is no such thing as depletion-load NMOS? That's weird man!

BTW, the following excerpt is taken from the paper Recollections of Early Chip Development at Intel by Andrew M. Volk, Peter A. Stoll and Paul Metrovich. "The 8085, 8086, and SRAMs used the same NMOS processes. In the mid-70s, the SRAM business was seen as a larger revenue source than the microprocessors. Tweaks were made to the process to improve SRAM performance without worrying about the impact on the microprocessors. Today, it would be strange to think that an SRAM process requirement was more important than a microprocessor design. A bit later, Intel developed its dual implant NMOS process called “HMOS” for high-speed SRAMs.".

HenkeB (talk) 03:58, 13 January 2009 (UTC)[reply]

<- Dual-implant is the (expensive) development which allowed depletion-mode transistors, and is not a "tweak." Being able to accurately align various implants is also the requisite for CMOS, so I'd expect HMOS to have been short-lived. I doubt the original 6800 had any depletion-mode xistors. Incidentally, microprocessor technologies are still optimized for and prototyped with SRAMs, as a sizable part of any MPU is SRAM cache.

Anyway, if you want to actually improve this article as it's tagged, or win this debate with me, you should probably add references. Potatoswatter (talk) 02:12, 14 January 2009 (UTC)[reply]

By the way, I don't want to take the silly position that depletion-load NMOS isn't a kind of NMOS… the force at play here is that adding the second implantation step was expensive, and no marketing department would miss out on the chance to attach the appropriate buzzword to their product. And, even if some products weren't marketed with the HMOS "brand," it was ubiquitous enough to become synonymous with the technology, and as Google shows, more widespread than the technical terms. So it is reasonable to call any such circuits HMOS. Potatoswatter (talk) 03:11, 14 January 2009 (UTC)[reply]

I agree with HenkeB. The whole article is totally misleading, at best. And of course that the original 6800 had depletion-load. What references do you want Potatoswatter? You are not going to find authoritative references because as you are saying, HMOS is mostly a marketing term. It is not a term that you would find in text books. You didn't provide any references either. Where you got the idea that HMOS is a synonymous (or become one) of depletion-load NMOS? That is almost ridiculous.

The plain truth is that HMOS in just one variant of depletion-load NMOS.Ijor (talk) 05:26, 23 March 2009 (UTC)[reply]