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Embedded Supercomputing

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This is an old revision of this page, as edited by DFS454 (talk | contribs) at 13:34, 19 March 2009 (Tagging Image:Embedded SC.JPG which is up for deletion per CSD). The present address (URL) is a permanent link to this revision, which may differ significantly from the current revision.

Embedded Supercomputing [1] a relatively new solution for handling fine grained and coarse grained parallelism to speed-up of the parallel application.

Basically Embedded Supercomputing is a hybrid network of CPU and FPGA hardware Where FPGA acts as external co-processor to CPU, however the programming model still evolving.


This file may be deleted after Thursday, 26 March 2009.

This file may be deleted after Thursday, 26 March 2009.


References

  1. ^ AVerentziotis, Evangelos (MARCH 2002). The EFTOS Approach to Dependability in Embedded Supercomputing. {{cite book}}: Check date values in: |year= (help); line feed character in |title= at position 48 (help)CS1 maint: year (link)
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