Jump to content

Page attribute table

From Wikipedia, the free encyclopedia
This is an old revision of this page, as edited by 92.232.150.252 (talk) at 22:14, 18 January 2009 (Processor Supplementary Capability). The present address (URL) is a permanent link to this revision, which may differ significantly from the current revision.

The Page Attribute Table (also known as Page Allocation Table) is a Processor Supplementary Capability extension to the page table format of certain x86 and x86-64 microprocessors. Like Memory Type Range Registers (MTRRs), they allow for fine-grained control over how areas of memory are cached.

Unlike MTRRs, which provide the ability to manipulate the behavior of caching for a limited number of fixed physical address ranges, Page Attribute Tables allow for such behavior to be specified on a per-page basis, greatly increasing the ability of the operating system to select the most efficient behavior for any given task.

See also