Talk:Depletion-load NMOS logic

Sources (Aug. 2008)

Hello

I have looked-up for references according to HMOS. All I've found is that it means the technologic level (see de.WP article) but no reference with the circuit topology cu --Biezl (talk) 17:36, 25 August 2008 (UTC)[reply]

Good point. I really should've been better about that. Unfortunately the single de wp ref is for a late-generation version and hence not a good into. The topology involved is implied by the term "depletion load": there is a load device (ie pseudo-NMOS) is a depletion-mode transistor. Google for depletion load for more info. Potatoswatter (talk) 20:42, 25 August 2008 (UTC)[reply]

Now I've visted a technical library and looked-up some books. I've found non who mentions HMOS, but always NMOS-logic with depletion load. One was written in english. Maybe you can find this in your library. Something I've recognized is that Intel_8080 had NMOS mit enhancement load and 6 µm size the orginal Intel_8086 was build using NMOS with depletion load and 3 µm size (compare HMOS I). So intel started with HMOS as depletion load was introduced.

Finally I can't definitly say what's correct. I think the article can be left as it is and hopefully someone finds more definite sources in future.

VLSI Design Techniques for Analog and Digital Circuits: Geiger, Allen, Strader ISBN:007100728-8 page 535

BTW: To clearify what we're talking about look at Image:Nmos depletion and.svg which shows circuit diagram. (actually NAND)

--Biezl (talk) 16:20, 16 September 2008 (UTC)[reply]

HMOS was used more as a marketing term than in technical journals, but lives on in history. Therefore I think it deserves an article. Neither term is uniquely "correct." Thanks for the image! As depletion mode transistors are no longer used in logic, it would be nice to clarify the symbols though. Potatoswatter (talk) 17:35, 16 September 2008 (UTC)[reply]

high performance nmos?

Hi! I don't mean to be rude or aggressive here, but, what (significant) stylistic errors did I introduce? And, shouldn't pure facts have somewhat higher priority than such stylistic details? Also, I was planning to add information later (and let others do the same), I didn't have the time to fix everything at once.

Most nMOS chips used depletion-load gates, only the very first nMOS designs (such as the 8080), used enhancement mode transistors as pullup, demanding +/-5V and 12V (the 8008 used pMOS). It is fairly clearly stated or implied in both datasheets (for 8086 etc) as well as in other documents (for instance, by 8086 designer Stephen Morse et al) that Intel's HMOS process is a variant on the depletion-load technique. I don't know exactly what it is that Motorola calls HMOS, but probably something similar. I belive depletion-load nMOS is a far more important encyclopedia entry than is HMOS, as the term is technically well defined and actually mean something in itself. (And why call depletion load nMOS "tuned" transistors etc?) HenkeB (talk) 20:52, 12 January 2009 (UTC)[reply]