Focal-plane array testing
(under development)
Focal Plane Array testing (FPA testing) is the test engineering process of validation and verification (V&V) of operation of focal plane array imaging devices, device under test (DUT), at various levels of the development and/or production assembly process. V&V can be done internal to the DUT (detector array and readout circuit), such as with built-in self-test (BIST) or external, such as with automatic test equipment. Functional and environmental testing is part of V&V. An FPA is basically composed of a photon or phonon detector array and a readout integrated circuit. There are basically five processing steps performed by these two sub-components, including: getting the electromagnetic energy in the detector; generating a consequent charge in the detector; charge collection; charge to voltage conversion; signal transfer; and digitization. Testing at various levels of the entire process can filter out FPA's with excessive number of unit cell defects before the complete process is carried out.
Overview
FPA testing (automated or semi-automated) utilizes hardware and software to characterize the DUT by measuring parameters such as: signal transfer function; signal transfer function vs differential temperature; spatial noise power spectral density; noise equivalent temperature difference; modulation transfer function; RMS and fixed pattern noise; temporal noise; responsivity and detectivity; spectral response; crosstalk; minimum resolvable temperature difference; intensification gain; field of view; spatial resolution; dynamic range; focus adjustment; harmonization; alignment; distortion.
Software analyses the DUT sensor images in real time, including array failure maps. Source temperature settings and target selection are computer-controlled. The software can integrate a complete test bench comprising collimator, source, optical table and data acquisition system.
Test & Evaluation primer
Management of Test and Evaluation
The Test and Evaluation process identifies levels of performance and assists the developer in correcting deficiencies. It is a significant element in the decision-making process providing data that support trade-off analysis, risk reduction, and requirements refinement. Program decisions on system performance maturity and readiness to advance to the next phase of development take into consideration demonstrated performance. The issue of paramount importance is: will it fulfill the mission? will it work? will it do what it was intended to do? The T&E process provides data that shows how the system is performing during development. The Program Manager must balance the risks of cost, schedule, and performance to keep the program on track. The responsibility of decision-making authorities centers on assessing risk tradeoffs.
Development Test and Evaluation
Development Test and Evaluation (DT&E) is conducted to demonstrate that the engineering design and development process is complete. It is used to reduce risk, validate and qualify the design, and ensure that the product is ready. The results are evaluated to ensure that design risks have been minimized and the system will meet specifications. DT&E serves a critical purpose in reducing the risks of development by testing selected high-risk components or subsystems. DT&E is a 2nd or 3rd party tool used to confirm that the system performs as technically specified and that the system is ready for field testing.
Operational Test and Evaluation
OT&E is conducted for major programs by an organization that is independent of the developing, procuring, and using commands. Some form of operational assessment is normally conducted in each acquisition phase. Each assessment should be keyed to a decision review in the material acquisition process. It should include typical user operators, crews, or units in realistic simulations of operational environments. The OT&E provides the decision authority with an estimate of: 1) The degree of satisfaction of the user’s requirements expressed as operational effectiveness and operational suitability of the new system; 2) The system’s desirability, considering equipment already available, and operational benefits or burdens associated with the new system; 3) The need for further development of the new system to correct performance deficiencies; 4) The adequacy of doctrine, organizations, operating techniques, tactics, and training for employment of the system; of maintenance support for the system; and of the system’s performance in the countermeasures environment.
Focal plane array primer
A focal plane array uses the infrared detector for the first step in digital imaging (detection of light and collection of photocharge into pixels). The circuits are fabricated with the same methods that produce computer chips, but special amplifiers are required to sense the small packets of photocharge produced by weak sources. The silicon readout integrated circuit converts the charge to voltage with an amplifier in each pixel, and transfers the signal to the edge of the array. The analog-to-digital conversion can be done on the imaging array, or in the focal plane electronics. The pixels of the detector array are attached to the pixels of the readout via Indium interconnects - one Indium bump per pixel. Since the readout multiplexes the signals from each pixel to the off-chip electronics, the readout is a multiplexer (one of many functions provided by the readout).
Detector
A focal-plane-array detector is any detector that has more than one row of detectors. The focal plane of an optical system is a point at which the image is focused. An array of detectors (FPA) is located at a point where the image is focused. Typical infrared FPA systems have an array of 256 x 256 detectors.
FPA detectors have high-resolution IR imaging capabilities. An array of detectors staring at the scene rather than a single detector being scanned across the scene means IR cameras can be much smaller, lighter, and more power efficient than a camera with elaborate scanning components.
Not all the surface of the detector is sensitive to IR energy. Around the rows and columns of individual IR detectors making up the array is an inactive region surrounding each of the detector. The inactive areas can serve as pathways for electronic signals. The ratio of active IR sensing material to inactive row and column borders is called the fill factor. An ideal detector would have a very high fill factor because it would have a large percentage of its area dedicated to collecting IR photons and a very small area dedicated to detector segregation. Typical infrared FPA systems have fill factors of 85%.
A camera with a high fill-factor detector will typically provide better sensitivity and overall image quality than one with a lower fill factor. High fill-factor detectors offer better cooling efficiency so less power is used to cool the detector to operating temperature.
There are two types of infrared FPAs: monolithic and hybrid. Monolithic FPAs have both IR-sensitive material and signal transmission paths on the same layer. Monolithic FPAs are easier and less expensive to manufacture than hybrids because fewer manufacturing steps are required. Monolithic FPAs have lower performance than hybrids because having the detector material and signal pathways on the same level results in a significantly lower fill factor.
The difference between a system with a monolithic FPA array and a hybrid array manifested in poorer image quality. This difference is noticeable when viewing low temperatures or small temperature differences. Hybrids have advanced features such as variable integration time.
A hybrid array has the IR-sensitive detector material on one layer and the signal-transmission and processing circuitry on another layer. The two layers are bonded together by small indium bumps which transmit the signal from each detector element to its respective signal path on the multiplexer below. Although this process requires more steps and can be more expensive, it results in FPAs with a significantly higher fill factor (85%-90%). The higher fill factor resulting from this geometry provides much higher sensitivity than usually found in corresponding monolithic FPAs.
The detector material is a key factor in array performance. Two primary measures are quantum efficiency and dark current. The best material is HgCdTe grown by molecular beam epitaxy. With substrate removal the HgCdTe responds to visible light and quantum efficiency can be increased for wide bandpass. This enables focal plane arrays to provide wide spectral sensitivity, ultraviolet to infrared.
Readout
After the photocharge has been collected into pixels the charge flows to the readout via indium bumps. A key aspect of the hybrid CMOS imager architecture is that the readout is fabricated with the same equipment that is used for making high performance integrated circuits. With the highly advanced tools used for IC design, the functionality of the readout is limited only by the designer and space constraints of the pixel. Space constraints can be overcome by using finer design rules. The most basic functionality of the pixel is charge-to-voltage conversion (photovoltaic) and transmission of the voltage signal off-chip. It is also possible to include signal processing within the pixel such as range detection or background subtraction. Hundreds of transistors within a pixel are possible.
There are two basic types of readout devices for taking each detector`s signal and getting it to the camera`s signal processor: a charge-coupled device (CCD) detector and a complementary metal-oxide semiconductor (CMOS) detector. The CCD detector operates in a mode in which the signal from each detector is determined by transferring its electrons from one detector to the next down the same row until it reaches the end column where it is read out. The CCD transfer process is not perfect because some of the charge is lost along the way (known as charge-coupled transfer loss phenomenon). Also, when one detector cell becomes overfilled with photons from a hot source, the photons can overflow into the adjacent detector cells (blooming). CCD detectors require significantly more power than their CMOS counterparts and thus usually require higher-power cooling devices.
CCD detectors are widely used in imaging applications because the losses encountered by the loss phenomenon and blooming are typically not relevant in non-measurement scenarios. When a CCD detector is used in a measurement infrared FPA camera the errors must be compensated.
A CMOS detector has a readout made up of a series of metal-oxide-silicon field-effect transistors that provide direct access to the signal from each detector. In a CMOS detector, the signal from each detector is read out column by column and row by row until each detector has been addressed individually and its exact value provided to the signal processor.
CMOS circuits are ideal for low-power applications. Power dissipation in a detector readout circuit is critical because it must be cooled with the detector to -200°C. Even with a highly efficient cooler, each milliwatt of power dissipated by the readout requires about 25 mW of battery power for cooling. Maximum battery life is achieved by using a CMOS multiplexer detector readout and high-efficiency rotary Stirling engine cooler. CMOS detectors provide better accuracy for measurements as a result of their direct access readout capability. A multiplexer is the device that organizes and formats the signals from each detector in a repeatable fashion. Typically, a multiplexer takes the signal from each individual detector and feeds it to a signal processor through one or more output devices.
FPA test and evaluation primer
1) Assist system development. Perform tests to verify system functionality and get key data for system hardware and software development. 2) Test piecemeal. Perform tests first to characterize performance at the subsystem level . Tests of multiple subsystems and their interfaces are based on experience at the subsystem level. Avoid testing at a high system level. Faults at this high level are difficult to isolate. 3) Isolate faults and troubleshoot. Detect and isolate faults in the system to reduce risk of failure in a costly higher-end test. Ensure the system meets its requirements. 4) Probe the system for likely vulnerabilities. Devise tests that realistically stress the system. These are tests beyond the acceptance tests performed at manufacturing level. 5) Integrate test and simulation. Simulations are important in evaluating system performance over the many scenarios that would be impractical to test. Integrating simulation development and test programs is a good practice. Simulation models are typically validated through testing as they are developed. Test data are used as inputs to define model parameters. 6) Provide rapid response and documentation. Respond quickly in investigating unexpected problems and devising solutions. Test results and analyses are typically documented either in the form of a report or a formal presentation within weeks. 7) Avoid using the system to test itself (except BIST). Using measurements from the device under test to gauge its own performance is a common practice. Unfortunately, there have been cases where these data were wrong leading to false test results and conclusions. Before such data are relied on during tests, it is standard practice to validate the data using external calibration devices. 8) Develop test facilities that emphasize flexibility, portability and expansion. Performance compromises should not be made in the test equipment to accommodate potential applications that might come later. Construct test equipment into modular building blocks that can be reconfigured, modified, or upgraded gradually. Provide flexibility for incremental testing.
DUT examples
- CCD, CID, CMOS, PDA
- Cryocooler/FPA
- Uncooled FPA
- Microbolometers
- SWIR FPA
- Dual-band FPA
- Readout integrated circuits
- Hyperspectral FPA
- Polarimetric FPA
- QWIP FPA
- InGaAs FPA
- HgCdTe FPA
Test equipment
Commercial automatic test equipment for FPA testing is very expensive (prober, parameter analyzer, etc). However, minimal production testing is possible on a boot-strap budget. A relatively low cost test system for testing non-uniformity and signal to noise (S/N) ratio of an uncooled focal plane array can use programmable logic devices to generate the necessary pulses for the DUT and low dropout regulator to obtain low noise bias. A proportional integral derivative (PID) thermoelectric cooler that is microprocessor or microcontroller controlled can stabilize the DUT. A PC-based data acquisition card can then be used as an analog-to-digital converter (ADC) to convert DUT output to digital input for computer analysis. The 12-bit ADC capability provides sufficient accuracy for evaluating the S/N ratio and non-uniformity of 128 x 128 pixels DUT. High level software is used to control test procedures and analyze the signals.
Test considerations
Testing focal plane arrays requires: 1) writing a concise test procedures with unambiguous system specifications; 2) identifying all appropriate test parameters; 3) differentiating between observer variability and system response during MRC and MRT testing; 4) understanding how jitter, linearity, amplitude normalization, frequency scaling, and noise affect CTF and MTF measurements; 5) discerning the difference between poor system performance, peculiarities of the system under test and measurement errors; and 6) understanding how sampling affects test results.
measurement techniques
(under development)Targets and collimators... differences between radiometry and photometry; define responsivity in radiometric, photometric, and differential temperature.
image resolution
(under development)Boundary detection...
responsivity
(under development)System response...differences between radiometry and photometry; define responsivity in radiometric, photometric, and differential temperature units (Radiometry/Photometry and System Responsivity) select appropriate equipment to measure responsivity identify possible causes of poor responsivity
noise
(under development)Thermal, shot... ergodicity; random, fixed pattern, and other noise components; nonuniformity; three-dimensional noise model; 3-D noise components vs. real noise sources; measurement techniques to quantify each noise component.
transfer functions
(under development)Linearity, fourier, modulation... CTF and MTF; MRT/MDT and MRC/MDC-why these metrics are a measure of image quality. Metrics considered include modulation transfer function (MTF), and contrast transfer function (CTF). For thermal imaging systems, image "quality" metrics include the minimum resolvable temperature (MRT) and minimum detectable temperature (MDT). For systems operating in the visible, these metrics become the minimum resolvable contrast (MRC) and minimum detectable contrast (MDC). Since all imaging systems spatially sample the scene, sampling artifacts occur in all imagery. Sampling effects become evident when viewing most test targets (typically bar patterns).
image quality
(under development)Subjective, objective criteria...
ergodicity
(under development)
chromatic aberration
(under development) Chromatic aberration is a phenomenon in which different wavelengths of light are not all focused at the same time. Chromatic aberration can occur in IR systems because systems sense energy over a wide range of wavelengths at one time. Without correction, energy at 3.5 µm might be focused and energy at 5.0 µm might be fuzzy. The resulting image would not be crisp and could be subject to measurement errors. Can correct for this by developing color-corrected IR lenses.
diffractive lenses
(under development) Diffractive lenses provide the color-correction capability of a set of multiple lenses with a single diffractive element. By doing the work of several lens elements with only a single element, the size, weight, and transmission properties of a lens can be improved. Diffractive lenses can be distinguished from standard lenses by the rings etched in the surface of the lens. These diffractive grooves cause lightwaves to be bent in a manner that corrects for chromatic aberration.
automation
(under development)Objectivity, productivity, reproducibility, ...
standardization
(under development)Role of industry organizations, SPIE...
statistical analysis
(under development)Objective vs subjective quality...
adjustable integration time
Integration time is the time that the FPA collects IR photons. An FPA runs at a maximum integration time of 16.7 ms (one complete frame). Arrays with adjustable integration time can capture photons over shorter periods of time. This reduces the amount of energy that the detector captures at any given temperature. FPAs with adjustable integration time have high-temperature imaging and measurement capabilities without needing filters. Some FPAs will operate at high temperatures by using an adjustable integration time. Adjustable integration time FPA's saves time because scenes at higher temperatures can be viewed by changing the electrical characteristics of the detector rather than installing an optical filter.
FPA Testing Using Dark Current
Dark current is the flow of charge in p-n junction under bias with no light. Since it is not possible to distinguish dark current from photocharge and since dark current has a Poisson noise distribution, very low dark current is required for sensing low illumination. Molecular beam epitaxy-made detectors have the lowest dark current of all mercad detectors. Dark current is a function of pixel area, temperature, and cutoff wavelength. Benefits of low dark current are: 1) enables the most sensitive flux measurements to be made at very cold temperatures; 2) enables operation at the highest temperature for a given level of performance, decreasing thermal load on the instrument cooling system.
With flip-chip technology a detector (focal plane array) can be hybridized to a readout integrated circuit with Indium bumps. A pre-binding test is needed on the FPA and readout, but conventional probe-testing is time comsuming and raises probe-related risks. Measuring the dark current of the photodiodes provides an alternative test technique. The off-current from the MOS switches, however, needs to be calibrated. A good approximation of the calibrated off-current (if the number of columns and rows are large) can be calculated. Use of a test socket chip to test detectors using dark current measurements with single automated probe that can cancel out calibrated off-current can be a useful alternative to conventional tests.
Camera System Testing
A camera systems includes packaged focal plane arrays with optics, cryocoolers, and board electronics with requirements from several engineering diciplines such as mechanical, optical, thermal, and electrical. Testing camera systems incorporate system-level tests which are appropriate with system engineering objectives. A camera test engineer may be responsible for development of functional test systems for visible and infrared cameras, and electronics; specifying and/or designing of test equipment, fixtures and tooling, setup and maintenance of image acquisition computers and lab instrumentation; settting up and maintenance of cryogenic and high vacuum systems required for integrated camera testing; setting up and using test equipment to perform testing and troubleshooting; locating and identifying problems at the sub-assembly level; participating in new product design to ensure Design For Test principles are incorporated, and in transfering test methods to manufacturing. Manufacturing test includes generating Test Plans, Test Procedures, Work Instructions, and general technical support to production.
Testing Challenges
- high density (small unit cells and large format arrays)
- small electrical currents (small unit cell)
- probe point impossibilities (flip chip technology)
- pre-binding test required
- conventional probe is time consuming
- MOS off-current calibration (dark current)
- serial vs parallel testing
- built-in current sources