Focal-plane array testing
(under development)
Focal Plane Array testing (FPA testing) is the test engineering process of validation and verification (V&V) of operation of focal plane array imaging devices, device under test (DUT), at various levels of the development and/or production assembly process. V&V can be done internal to the DUT (detector array and readout circuit), such as with Built-In Test Equipment or external, such as with automatic test equipment. Functional and environmental testing is part of V&V. An FPA is basically composed of a photon or phonon detector array and a readout integrated circuit. There are basically five processing steps performed by these two sub-components, including: getting the electromagnetic energy in the detector; generating a consequent charge in the detector; charge collection; charge to voltage conversion; signal transfer; and digitization. Testing at various levels of the entire process can filter out FPA's with excessive number of unit cell defects before the complete process is carried out.
Overview
FPA testing (automated or semi-automated) utilizes hardware and software to characterize the DUT by measuring parameters such as: signal transfer function; signal transfer function vs differential temperature; spatial noise power spectral density; noise equivalent temperature difference; modulation transfer function; RMS and fixed pattern noise; temporal noise; responsivity and detectivity; spectral response; crosstalk; minimum resolvable temperature difference; intensification gain; field of view; spatial resolution; dynamic range; focus adjustment; harmonization; alignment; distortion.
Software analyses the DUT sensor images in real time, including array failure maps. Source temperature settings and target selection are computer-controlled. The software can integrate a complete test bench comprising collimator, source, optical table and data acquisition system.
Test & Evaluation primer
Management of Test and Evaluation
The Test and Evaluation process identifies levels of performance and assists the developer in correcting deficiencies. It is a significant element in the decision-making process providing data that support trade-off analysis, risk reduction, and requirements refinement. Program decisions on system performance maturity and readiness to advance to the next phase of development take into consideration demonstrated performance. The issue of paramount importance is: will it fulfill the mission? will it work? will it do what it was intended to do? The T&E process provides data that shows how the system is performing during development. The Program Manager must balance the risks of cost, schedule, and performance to keep the program on track. The responsibility of decision-making authorities centers on assessing risk tradeoffs.
Development Test and Evaluation
Development Test and Evaluation (DT&E) is conducted to demonstrate that the engineering design and development process is complete. It is used to reduce risk, validate and qualify the design, and ensure that the product is ready. The results are evaluated to ensure that design risks have been minimized and the system will meet specifications. DT&E serves a critical purpose in reducing the risks of development by testing selected high-risk components or subsystems. DT&E is a 2nd or 3rd party tool used to confirm that the system performs as technically specified and that the system is ready for field testing.
Operational Test and Evaluation
OT&E is conducted for major programs by an organization that is independent of the developing, procuring, and using commands. Some form of operational assessment is normally conducted in each acquisition phase. Each assessment should be keyed to a decision review in the material acquisition process. It should include typical user operators, crews, or units in realistic simulations of operational environments. The OT&E provides the decision authority with an estimate of: 1) The degree of satisfaction of the user’s requirements expressed as operational effectiveness and operational suitability of the new system; 2) The system’s desirability, considering equipment already available, and operational benefits or burdens associated with the new system; 3) The need for further development of the new system to correct performance deficiencies; 4) The adequacy of doctrine, organizations, operating techniques, tactics, and training for employment of the system; of maintenance support for the system; and of the system’s performance in the countermeasures environment.
Focal plane array primer
A focal plane array uses the infrared detector for the first step in digital imaging (detection of light and collection of photocharge into pixels). The circuits are fabricated with the same methods that produce computer chips, but special amplifiers are required to sense the small packets of photocharge produced by weak sources. The silicon readout integrated circuit converts the charge to voltage with an amplifier in each pixel, and transfers the signal to the edge of the array. The analog-to-digital conversion can be done on the imaging array, or in the focal plane electronics. The pixels of the detector array are attached to the pixels of the readout via Indium interconnects - one Indium bump per pixel. Since the readout multiplexes the signals from each pixel to the off-chip electronics, the readout is a multiplexer (one of many functions provided by the readout).
Detector
The detector material is a key factor in array performance. Two primary measures are quantum efficiency and dark current. The best material is HgCdTe grown by molecular beam epitaxy. With substrate removal the HgCdTe responds to visible light and quantum efficiency can be increased for wide bandpass. This enables focal plane arrays to provide wide spectral sensitivity, ultraviolet to infrared.
Readout
After the photocharge has been collected into pixels the charge flows to the readout via indium bumps. A key aspect of the hybrid CMOS imager architecture is that the readout is fabricated with the same equipment that is used for making high performance integrated circuits. With the highly advanced tools used for IC design, the functionality of the readout is limited only by the designer and space constraints of the pixel. Space constraints can be overcome by using finer design rules. The most basic functionality of the pixel is charge-to-voltage conversion (photovoltaic) and transmission of the voltage signal off-chip. It is also possible to include signal processing within the pixel such as range detection or background subtraction. Hundreds of transistors within a pixel are possible.
DUT examples
- CCD, CID, CMOS, PDA
- Cryocooler/FPA
- Uncooled FPA
- Microbolometers
- SWIR FPA
- Dual-band FPA
- Readout integrated circuits
- Hyperspectral FPA
- Polarimetric FPA
- QWIP FPA
- InGaAs FPA
- HgCdTe FPA
Test equipment
Commercial automatic test equipment for FPA testing is very expensive (prober, parameter analyzer, etc). However, minimal production testing is possible on a boot-strap budget. A relatively low cost test system for testing non-uniformity and signal to noise (S/N) ratio of an uncooled focal plane array can use programmable logic devices to generate the necessary pulses for the DUT and low dropout regulator to obtain low noise bias. A proportional integral derivative (PID) thermoelectric cooler that is microprocessor or microcontroller controlled can stabilize the DUT. A PC-based data acquisition card can then be used as an analog-to-digital converter (ADC) to convert DUT output to digital input for computer analysis. The 12-bit ADC capability provides sufficient accuracy for evaluating the S/N ratio and non-uniformity of 128 x 128 pixels DUT. High level software is used to control test procedures and analyze the signals.
Test considerations
measurement techniques
(under development)Targets and collimators...
image resolution
(under development)Boundary detection...
responsivity
(under development)System response...
noise
(under development)Thermal, shot...
transfer functions
(under development)Linearity, fourier, modulation...
image quality
(under development)Subjective, objective criteria...
automation
(under development)Objectivity, productivity, reproducibility, ...
standardization
(under development nov 08)Role of industry organizations, SPIE...
statistical analysis
(under development)Objective vs subjective quality...
FPA Testing Using Dark Current
Dark current is the flow of charge in p-n junction under bias with no light. Since it is not possible to distinguish dark current from photocharge and since dark current has a Poisson noise distribution, very low dark current is required for sensing low illumination. Molecular beam epitaxy-made detectors have the lowest dark current of all mercad detectors. Dark current is a function of pixel area, temperature, and cutoff wavelength. Benefits of low dark current are: 1) enables the most sensitive flux measurements to be made at very cold temperatures; 2) enables operation at the highest temperature for a given level of performance, decreasing thermal load on the instrument cooling system.
With flip-chip technology a detector (focal plane array) can be hybridized to a readout integrated circuit with Indium bumps. A pre-binding test is needed on the FPA and readout, but conventional probe-testing is time comsuming and raises probe-related risks. Measuring the dark current of the photodiodes provides an alternative test technique. The off-current from the MOS switches, however, needs to be calibrated. A good approximation of the calibrated off-current (if the number of columns and rows are large) can be calculated. Use of a test socket chip to test detectors using dark current measurements with single automated probe that can cancel out calibrated off-current can be a useful alternative to conventional tests.
Testing challenges
- high density (small unit cells and large format arrays)
- small electrical currents (small unit cell)
- probe point impossibilities (flip chip technology)
- pre-binding test required
- conventional probe is time consuming
- MOS off-current calibration (dark current)
- serial vs parallel testing
- built-in current sources