Single-cycle processor
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MIPS-32 Instruction set
Instruction sets are classified in to the following groups that can perform almost every operation.
R-format
This type of instruction format can perform ALU and Register operations listed below.
• Add
• Subtract
• AND
• OR
• XOR
• Less than
• Greater than (etc)
Opcode is used to guide the control unit and distinguish instruction types.
RS is the Source register address (5-bits).
RT is the Target register address (5-bits).
RD is the Destination register address (5-bits).
Func field distinguishes between ALU operations.
EXAPMLE:
ADD $R1,$R2,$R3
SUB $R1,$R2,$R3
AND $R1,$R2,$R3
I-type instruction:
This type of instruction involves the data memory base address and offset are used to calculate the exact memory address.
Following types of instructions can be carried out
• LW (Load word)
• SW (store word)
• ALU Immediate
• BEQ (Branch if Equal)
• BNE (Branch if not Equal)
RS is the register containing the memory base address.
RT in this case is used as Destination register.
Offset field is the memory offset at which the data is placed.
EXAPMLE:
BNE $R1,$R2,target
LW $R1,$R2($R3)
SW $R1,$R2($R3)
J-type instruction:
This type of instruction can perform unconditional jumps, relative to the current address in the program counter.
File:Jformat.jpg
Offset field consist of the jump offset.
EXAMPLE:
J target
Single Cycle MIPS 32 Processor Components
Register File:
The register file consists of 32 Registers of 32-bits in length. RS, RT, RD are 5-bits address; the data on addresses RS and RT will be available on RS Out and RD out (32-bits). The data available on Data In will be written on the address RD (5-bits).
File:Regfile.jpg
ALU (Arithmetic and Logic Unit):
The ALU can perform all the arithmetic and logical operations (ADD, SUB, AND, OR, XOR, SLG, SGT, etc).
File:Alu.jpg
DATA Memory:
The DATA memory holds the Data to be processed (32-bits).A word can be loaded and stored into this memory based on instruction
File:Datamem.jpg
Instruction Memory:
The Instruction memory holds the instructions to be processed (32-bits).
Single Cycle Data Path:
File:Single cycle cpu datapath.png
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