Altos Design Automation
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Overview
Altos Design Automation, Inc. provides ultra-fast, fully automated, characterization technology for the creation of library views for timing, signal integrity and power analysis and optimization. Altos’ advanced modeling solutions are used by both corner-based and statistical-based design implementation flows to reduce time to market and improve yield.
Privately held, Altos was founded in January 2005 in Santa Clara, CA by former employees of Cadence Design Systems. All members of the team worked at CadMOS where they were responsible for the development of Signal Integrity analysis tools for both cell- and transistor-level digital IC designers.
Its corporate headquarters is at 4020 Moorpark Ave., Suite 100, San Jose, CA 95117. Telephone: (408) 980-8056.
Products
Variety™ Variety creates statistical timing cell models that represent the non-linear impact of any number of systematic and random parameter variations. All library timing data is characterized for variation including delays, transitions, timing constraints, and pin capacitances. Variety generates SSTA models for a number of commercial SSTA products from a single characterization run.
Liberate™ Liberate is an automated library characterization tool for standard cells and I/Os that serves existing static timing analyzers. Liberate takes in a Spice netlist and Spice subcircuits, and automatically generates a characterized cell library. It supports both Composite Current Source (CCS) model backed by Synopsys and the Effective Current Source Model (ECSM) backed by Cadence Design Systems.
References
- "Fireside Chat: Rick Lucier and Jim McCanny", EDACafe, 2008-01-28.
- "The 'Inconvenient Truth' of statistical design", SCDsource, 2007-12-05.
- "Where's the value in DFM? D or M?", Chip Design, 2007-03-01.
- "Statistical timing gets modeling boost", EE Times, 2007-01-15.
- "Characterization tool aids SSTA-library creation", EDN, 2007-01-15.
- "Altos closes $1.5M, signs Jim Hogan", EE Times, 2007-01-05.
- "Firms partner on standard statistical analysis library format", EE Times, 2006-07-25.
- "What's Hot at DAC?", EE Times, 2006-07-17.
- "Startup to 'Liberate' library characterization", EE Times, 2006-07-03.
- "Statistical timing revs for 45-nm era", EE Times, 2006-07-03.
- "Altos Targets Statistical Timing Models", Electronic News, 2006-07-03.