Talk:Depletion-load NMOS logic
Sources (Aug. 2008)
Hello
I have looked-up for references according to HMOS. All I've found is that it means the technologic level (see de.WP article) but no reference with the circuit topology cu --Biezl (talk) 17:36, 25 August 2008 (UTC)
- Good point. I really should've been better about that. Unfortunately the single de wp ref is for a late-generation version and hence not a good into. The topology involved is implied by the term "depletion load": there is a load device (ie pseudo-NMOS) is a depletion-mode transistor. Google for depletion load for more info. Potatoswatter (talk) 20:42, 25 August 2008 (UTC)
- Now I've visted a technical library and looked-up some books. I've found non who mentions HMOS, but always NMOS-logic with depletion load. One was written in english. Maybe you can find this in your library. Something I've recognized is that Intel_8080 had NMOS mit enhancement load and 6 µm size the orginal Intel_8086 was build using NMOS with depletion load and 3 µm size (compare HMOS I). So intel started with HMOS as depletion load was introduced.
- Finally I can't definitly say what's correct. I think the article can be left as it is and hopefully someone finds more definite sources in future.
- VLSI Design Techniques for Analog and Digital Circuits: Geiger, Allen, Strader ISBN:007100728-8 page 535
- BTW: To clearify what we're talking about look at Image:Nmos depletion and.svg which shows circuit diagram. (actually NAND)
