Structured ASIC platform
It is proposed that this article be deleted because of the following concern:
If you can address this concern by improving, copyediting, sourcing, renaming, or merging the page, please edit this page and do so. You may remove this message if you improve the article or otherwise object to deletion for any reason. Although not required, you are encouraged to explain why you object to the deletion, either in your edit summary or on the talk page. If this template is removed, do not replace it. This message has remained in place for seven days, so the article may be deleted without further notice. Find sources: "Structured ASIC platform" – news · newspapers · books · scholar · JSTOR Nominator: Please consider notifying the author/project: {{subst:proposed deletion notify|Structured ASIC platform|concern=Appears to be non-notable technology currently in development, written in an advertising style. Tons of sources, but publications not listed.}} ~~~~Timestamp: 20080830214833 21:48, 30 August 2008 (UTC) Administrators: delete |
Structured ASIC is an intermediate technology between ASIC and FPGA, offering high performance, a characteristic of ASIC, and low NRE cost, a characteristic of FPGA. Using Structured ASIC allows products to be introduced quickly to market, to have lower cost and to be designed with ease.
Work at CUHK:
A structured ASIC research project in on-going at CUHK, the main research and development work in this project includes:
- study methods to map quickly a FPGA design to a Programmable Fabric, and develop corresponding EDA tools.
- design a Programmable Fabric.
- integrate the Programmable Fabric with a highly flexible and configurable SoC ASIC, to realize an IC design and verification platform that offers short time-to-market and low design cost.
The objective is to open new opportunity in Programmable Logic Device market based on Structured ASIC. The platform developed will be quick and easy to use, will represent low risk in design and testing, hence, will benefit IC design houses in both Hong Kong and Shenzhen. The dramatic reduction in design and testing cost means its market potential can be far and wide.
Deliverables
This project involves three parties (ASTRI, PKU, CUHK) and the co-operations between Shenzhen and Hong Kong SAR.
Hong Kong SAR:
- FPGA to Programmable Fabric instant mapping solution
- Programmable Fabric design, library development and EDA design tool/flow
- Structured ASIC design framework and platform integrating Soc and Programmable Fabric
- Structured ASIC application development board design framework
Shenzhen:
- Structured ASIC domain specific SoC design solution. The SoC will have ARM/MIPS core, AMBA bus, optional IP cores and user defined Programmable Fabric; targeted applications include telecommunication terminals, LCD TV peripheries and even handset prototype development and verification. The embedded Gate Array will have different configurations to meet users' different logic requirements.
- Structured ASIC silicon
- Structured ASIC application development board targeting Shenzhen enterprises. The development board will support domain specific application development. With instant mapping of user defined FPGA to the embedded Programmable Fabric in the SoC, users not only can speed up their fast prototyping verification and SoC silicon development effort but can lower the overall cost. The board will have memory devices, and physical interface and connectors to external devices along with FPGA to Gate Array mapping tool, third party C/C++ compiler, simulator and emulator.
References
- Steve Wilton et al. - "A Synthesizable Datapath-Oriented Embedded FPGA Fabric"
- Chun Hok Ho et al. - "Floating Point FPGA: Architecture and Modelling"
- Andy Ye and Jonathan Rose - "Using Bus-Based Connections to Improve Field-Programmable Gate Array Density for Implementing Datapath Circuits"
- Ian Kuon, Aaron Egier and Jonathan Rose - "Design, Layout and Verification of an FPGA using Automated Tools"
- Chun Hok Ho et al. - "DOMAIN-SPECIFIC HYBRID FPGA: ARCHITECTURE AND FLOATING POINT APPLICATIONS"
- Ian Kuon, Russell Tessier and Jonathan Rose - "FPGA Architecture: Survey and Challenges"
- Steve Wilton et al. - "A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications"
- Ian Kuon and Jonathan Rose - "Measuring the Gap Between FPGAs and ASICs"
- Altera Corp - "HardCopy II Structured ASICs"
- Stephane Badel and Elizabeth J. Brauer - "Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells"
- Kanupriya Gulati, Nikhil Jayakumar and Sunil P. Khatri - "A Structured ASIC Design Approach Using Pass Transistor Logic"
- Hee Kong Phoon, Matthew Yap and Chuan Khye Chai - "A Highly Compatible Architecture Design for Optimum FPGA to Structured-ASIC Migration"
- Yajun Ran and Malgorzata Marek-Sadowska - "Designing Via-Configurable Logic Blocks for Regular Fabric"
- R. Reed Taylor and Herman Schrnit - "Creating a Power-aware Structured ASIC"
- Jennifer L. Wong, Farinaz Kourshanfar and Miodrag Potkonjak - "Flexible ASIC: Shared Masking for Multiple Media Processors"