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Talk:Depletion-load NMOS logic

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This is an old revision of this page, as edited by Potatoswatter (talk | contribs) at 20:42, 25 August 2008 (reply). The present address (URL) is a permanent link to this revision, which may differ significantly from the current revision.

Sources (Aug. 2008)

Hello

I have looked-up for references according to HMOS. All I've found is that it means the technologic level (see de.WP article) but no reference with the circuit topology cu --Biezl (talk) 17:36, 25 August 2008 (UTC)[reply]

Good point. I really should've been better about that. Unfortunately the single de wp ref is for a late-generation version and hence not a good into. The topology involved is implied by the term "depletion load": there is a load device (ie pseudo-NMOS) is a depletion-mode transistor. Google for depletion load for more info. Potatoswatter (talk) 20:42, 25 August 2008 (UTC)[reply]
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