Structured ASIC platform

Structured ASIC is an intermediate technology between ASIC and FPGA, offering high performance, a characteristic of ASIC, and low NRE cost, a characteristic of FPGA. Using Structured ASIC allows products to be introduced quickly to market, to have lower cost and to be designed with ease.

Work at CUHK:

A structured ASIC research project in on-going at CUHK, the main research and development work in this project includes:

1. study methods to map quickly a FPGA design to a Programmable Fabric, and develop corresponding EDA tools.
2. design a Programmable Fabric.
3. integrate the Programmable Fabric with a highly flexible and configurable SoC ASIC, to realize an IC design and verification platform that offers short time-to-market and low design cost.

The objective is to open new opportunity in Programmable Logic Device market based on Structured ASIC. The platform developed will be quick and easy to use, will represent low risk in design and testing, hence, will benefit IC design houses in both Hong Kong and Shenzhen. The dramatic reduction in design and testing cost means its market potential can be far and wide.

Deliverables

This project involves three parties (ASTRI, PKU, CUHK) and the co-operations between Shenzhen and Hong Kong SAR.

Hong Kong SAR:

1. FPGA to Gate Array instant mapping solution
2. Gate Array design, library development and EDA design tool/flow
3. Structured ASIC design framework and platform integrating Soc and Gate Array
4. Structured ASIC application development board design framework

Shenzhen:

1. Structured ASIC domain specific SoC design solution. The SoC will have ARM/MIPS core, AMBA bus, optional IPs and user defined Gate Array; targeted applications include telecommunication terminals, LCD TV peripheries and even handset prototype development and verification. The embedded Gate Array will have different configurations to meet users' different logic requirements.
2. Structured ASIC silicon
3. Structured ASIC application development board targeting Shenzhen enterprises. The development board will support domain specific application development. With instant mapping of user defined FPGA to the embedded Gate Array in the SoC, users not only can speed up their fast prototyping verification and SoC silicon development effort but can lower the overall cost. The board will have memory devices, and physical interface and connectors to external devices along with FPGA to Gate Array mapping tool, third party C/C++ compiler, simulator and emulator.