SystemVerilog
SystemVerilog is a hardware description language based on Verilog. Although it has some features to assist with design, the thrust of the language is in verification of electronic designs. The bulk of the verification functionality is based on the OpenVera language donated by Synopsys. SystemVerilog is undergoing final approval to become an IEEE standard.
SystemVerilog is an extension of Verilog-2001; all features of that language are available in SystemVerilog. The remainder of this article discusses the features of SystemVerilog not present in Verilog-2001.
Design features
New data types
Multidimensional packed arrays unify and extend Verilog's notion of "registers" and "memories":
reg [1:0][2:0] my_var[32];
Classical Verilog permitted only one dimension to be declared to the left of the variable name. SystemVerilog permits any number of such "packed" dimensions. A variable of packed array type maps 1:1 onto an integer arithmetic quantity. In the example above, each element of my_var may be used in expressions as a six-bit integer. The dimensions to the right of the name (32 in this case) are referred to as "unpacked" dimensions. As in Verilog-2001, any number of unpacked dimensions is permitted.
Enumerated data types allow numeric quantities to be assigned meaningful names. Variables declared to be of enumerated type cannot be assigned to variables of a different enumerated type without casting. This is not true of parameters, which were the preferred implementation technique for enumerated quantities in Verilog-2001:
typedef enum reg [2:0] {
RED, GREEN, BLUE, CYAN, MAGENTA, YELLOW
} color_t;
color_t my_color = GREEN;
As shown above, the designer can specify an underlying arithmetic type (reg [2:0] in this case) which is used to represent the enumeration value. The meta-values X and Z can be used here, possibly to represent illegal states.
New integer types: SystemVerilog defines byte, shortint, int and longint as two-state integral types having 8, 16, 32 and 64 bits respectively. A bit type is a variable-width two-state type that works much like reg. Two-state types lack the X and Z metavalues of classical Verilog; working with these types may result in faster simulation.
Structures and unions work much like they do in theC programming language. A SystemVerilog enhancement is the packed attribute, which causes the structure or union to be mapped 1:1 onto a packed array of bits:
typedef struct packed {
bit [10:0] expo;
bit sign;
bit [51:0] mant;
} FP;
FP zero = 64'b0;
Unique/priority if/case
The unique attribute on a cascaded if or case statement indicates that exactly one branch or case item must execute; it is an error otherwise. The priority attribute on an if or case statement indicates that the choices are to be considered in order, but some branch must execute. These features enforce at simulation time the properties often declared by the de-facto synopsys full_case parallel_case annotations for use during synthesis.
Procedural blocks
In addition to Verilog's always block, SystemVerilog offers new procedural blocks that better convey the intended design structure. EDA tools can verify that the behavior described is really that which was intended.
An always_comb block creates combinational logic. The simulator infers the sensitivity list from the contained statements:
always_comb begin
tmp = b * b - 4 * a * c;
no_root = (tmp < 0);
end
An always_ff block is meant to infer synchronous logic:
always_ff @(posedge clk)
count <= count + 1;
An always_latch block is meant to infer a level-sensitive latch. Again, the sensitivity list is inferred from the code:
always_latch
if (en) q <= d;
Vefification features
The following verification features are typically not synthesizable. Instead, they assist in the creation of extensible, flexible test benches.
New data types
The string data type represents a variable-length text string.
In addition to the static array used in design, SystemVerilog offers dynamic arrays, associative arrays and queues:
int da[]; // dynamic array
int da[string]; // associative array, indexed by string
int da[$]; // queue
initial begin
da = new[16]; // Create 16 elements
end
A dynamic array works much like an unpacked array, but it must be dynamically created as shown above. The array can be resized if needed. An associative array can be thought of as a binary search tree with a user-specified key type and data type. The key implies an ordering; the elements of an associative array can be read out in lexicographic order. Finally, a queue provides much of the functionality of the C++ STL deque type: elements can be added and removed from either end efficiently. These primitives allow the creation of complex data structures required for scoreboarding a large design.
Classes
SystemVerilog provides an object-oriented programming model.
Constrained random generation
Integer quantities, defined either in a class definition or as stand-alone variables in some lexical scope, can be assigned random values based on a set of constraints. This feature is useful for creating randomized scenarios for verification.
Assertions
SystemVerilog has its own assertion specification language, similar to Property specification language. Assertions are useful for verifying properties of a design that manifest themselves over time.
Coverage
Coverage as applied to hardware verification languages refers to the collection of statistics based on sampling events within the simulation. Coverage is used to determine when the device under test (DUT) has been exposed to a sufficient variety of stimuli that there is a high confidence that the DUT is functioning correctly.