Massively parallel processor array

The Massively Parallel Processor Array (MPPA) is a class of integrated circuits which have a massively parallel array of hundreds to thousands of CPUs and RAMs, interconnected by a reconfigurable interconnect of word-wide channels. One or more CPUs and RAMs are combined with interconnect into a tile. Many tiles are stacked up to form the array.

MPPA is a MIMD (Multiple Instruction streams, Multiple Data) architecture, with distributed memory accessed locally, not shared globally. Each processor is strictly encapsulated, accessing only its own code and memory. Point-to-point communication between processors is directly realized in the configurable interconnect.

The MPPA's massive parallelism and its distributed memory MIMD architecture distinguishes it from multicore and manycore architectures, which have fewer processors and an SMP or other shared memory architecture, used for general-purpose computing, and from GPGPUs with SIMD architectures, used for HPC applications.

MPPAs are used in high-performance embedded systems and hardware acceleration of desktop computer and server applications, such as video compression, image processing, medical imaging, network processing, software defined radio and other compute-intensive streaming media applications, which otherwise would use FPGA, DSP and/or ASIC chips.

An MPPA application is developed by expressing it as a hierarchical block diagram or workflow, whose basic objects run in parallel, each on their own processor. Likewise, large data objects may be broken up and distributed into local memories with parallel access. Objects communicate over a parallel structure of dedicated channels. The objective is to maximize aggregate throughput while minimizing local latency, optimizing performance and efficiency. An MPPA's model of computation is similar to a Kahn process network or Communicating_sequential_processes (CSP).

MPPAs include commercial devices from Ambric, picoChip and IntellaSys, and the ASAP research chip.