Altos Design Automation
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Overview
Altos Design Automation, Inc. provides ultra-fast, fully automated, characterization technology for the creation of library views for timing, signal integrity and power analysis and optimization. Altos’ advanced modeling solutions are used by both corner-based and statistical-based design implementation flows to reduce time to market and improve yield.
Privately held, Altos was founded in January 2005 in Santa Clara, CA by former employees of Cadence Design Systems. All members of the team worked at CadMOS where they were responsible for the development of Signal Integrity analysis tools for both cell- and transistor-level digital IC designers.
Its corporate headquarters is at 4020 Moorpark Ave., Suite 100, San Jose, CA 95117. Telephone: (408) 980-8056.
Products
Variety™ Variety creates statistical timing cell models that represent the non-linear impact of any number of systematic and random parameter variations. All library timing data is characterized for variation including delays, transitions, timing constraints, and pin capacitances. Variety generates SSTA models for a number of commercial SSTA products from a single characterization run.
Liberate™ Liberate is an automated library characterization tool for standard cells and I/Os that serves existing static timing analyzers. Liberate takes in a Spice netlist and Spice subcircuits, and automatically generates a characterized cell library. It supports both Composite Current Source (CCS) model backed by Synopsys and the Effective Current Source Model (ECSM) backed by Cadence Design Systems and Magma Design Automation.
Founding Team
Jim McCanny, CEO & Founder - Prior to Altos, Jim was the Timing and Signal Integrity Marketing Group Director at Cadence. He was the VP of Marketing and Business Development at CadMOS when they were acquired by Cadence in 2001. Before CadMOS, Jim was Executive VP at Ultima Interconnect Technology (which as Celestry was acquired by Cadence in 2003), Major Account Technical Program Account Manager at EPIC Design Technology (which IPO'ed in 1994) and a Member of Group Technical Staff at Texas Instruments. Jim holds a BS in Math/Computer Science from Manchester, UK and has over 25 years experience in EDA.
Ken Tseng, CTO & Founder - Prior to founding Altos, Ken was a Cadence Architect responsible for signal integrity analysis tools PacifIC and CeltIC. At CadMOS, Ken was an R&D Director and the original author of CeltIC. Prior to that, he held R&D positions at Synopsys, Logic Modeling, Zycad and AMD. Ken holds multiple patents in timing, signal integrity and microprocessor design. He is an expert in circuit analysis, logic abstraction and signal integrity. He holds an MSEE/BSEE from UT Austin and has 20 years experience in EDA.
Kevin Chou, VP R&D & Founder - Kevin was a Senior Member of Consulting Staff at Cadence prior to founding Altos, responsible for the signal integrity closure flow in SoC Encounter. At CadMOS he was responsible for RLC interconnect analysis and CeltIC's cell noise library creation (cdB). Prior to CadMOS, Kevin held research positions at Princeton University, the Army High Performance Computing Research Center and Cornell Medical School. Kevin received his BSEE with summa cum laude from Cooper Union and his MSEE from Stanford University. Kevin has 10 years experience in EDA.
Doug Roston, VP Applications - Doug was the Director of Core Comp for Signal Integrity at Cadence where he supported the Encounter Timing System, CeltIC, PacifIC, VoltageStorm, and Fire & Ice. At CadMOS he was the Applications Manager responsible for supporting world wide sales. Prior to CadMOS, Doug worked at Epic Design Technology where he supported major accounts. Doug has 25 years experience working in test, design and applications engineering with 20 years of that in EDA. Doug has a Bachelors degree in Mathematics and Computer Science from Vanderbilt University.
References
- "Fireside Chat: Rick Lucier and Jim McCanny", "EDACafe", 2008-01-21.
[1]
SCDsource: The 'Inconvenient Truth' of statistical design
[2] Chip Design: Where's the value in DFM? D or M?
[3] EE Times: Statistical timing gets modeling boost
[4] EDN: Characterization tool aids SSTA-library creation
[5] EE Times: Altos closes $1.5M, signs Jim Hogan
[6] EE Times: Firms partner on standard statistical analysis library format
[7] EE Times: What's Hot at DAC?
[8] EE Times: Startup to 'Liberate' library characterization
[9] EE Times: Statistical timing revs for 45-nm era
[10] Electronic News: Altos Targets Statistical Timing Models
External links
www.altos-da.com