Digital clock manager
Digital Clock Manager is a function for manipulating clock signals by: [1]
- Multiply or divide an incoming clock.
- Recondition a clock, to for example ensure 50% duty cycle.
- Phase shift.
- Eliminate clock skew.
References
- ^ "Using Digital Clock Managers (DCMs) in Spartan-3 FPGAs" (PDF). 070804 xilinx.com