Source-synchronous
Source-Synchronous clocking refers to the technique of sourcing a clock along with the data. Specifically, the timing of unidirectional data signals is referenced to a clock (often called the strobe) sourced by the same device that generates those signals, and not to a global clock (i.e. generated by a bus master).
This type of clocking is common in high-speed interfaces between micro-chips, including DDR SDRAM interfaces (and variations, DDR2, RLDRAM, DDR3), SGI XIO interface, Intel Front Side Bus for the x86 and Itanium processors, HyperTransport, SPI-4.2 and many others.
Reasons for usage
A reason that source-synchronous clocking is useful is that it has been observed that all of the circuits within a given semiconductor device experience roughly the same process-voltage-temperature (PVT) variation. This means signal propagation delay experienced by the data through a device tracks the delay experienced by the clock through that same device over PVT. This advantage allows higher speed operation as compared to the traditional technique of providing the clock from a third device to both the transmitter and the receiver. Another benefit is that higher complexity data-recovery or clock-data-recovery circuits (such as PLLs) are not required when this technique is used.
Or rather than higher clock speeds, large systems that take advantage of source-synchronous clocking can have the benefit of a higher tolerance of PVT variation of its individual components.
Drawbacks
One drawback of using source-synchronous clocking is the creation of a separate clock-domain, namely the clock-domain of the strobe generated by the transmitting device. This strobe clock-domain are more often not synchronous to the core clock domain of the receiving device. For proper operation of the received data with other data already present in the device, an additional stage of synchronization logic will be required to transfer the received data into the core clock-domain of the receiving device. This stage can often be found along side with source synchronous logic. This usually results in greater system complexity compared to globally-clocked systems, but the benefits are generally much greater than this increase in complexity.
See Also
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