Talk:Single instruction, multiple threads

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Does 'SIMT' Include Latency-Hiding?

Should we consider 'SIMT' to include the latency-hiding strategy used by its current-day implementations, whereby different warps can be switched between with zero overhead?

One could construct a SIMT architecture which did not have this scheduling strategy, after all (as, say, an extension to an ordinary CPU architecture), but this scheduling strategy is central to the way SIMT is used today.

For now, I've assumed it is to be included in 'SIMT', and have made this change accordingly: 28 August 2014‎.

Wootery (talk) 17:16, 28 August 2014 (UTC)[reply]

Did NVidia Invent SIMT?

In their processor just before the ZMS-05, 3DLabs (now ZiiLabs) used SIMT, which (to me) is just SIMD with some paths disabled some of the time, and converting to a jump if they are all disabled. Who was first to use SIMT? — Preceding unsigned comment added by Nickpelling (talk • contribs) 10:21, 18 November 2018 (UTC)[reply]

yyeah i don't really know, it's a very good question. with all the history of computing that dates all the way back to the 50s, i doubt very much that nvidia invented SIMT. but you do have to be very careful about architectures. SIMD is most emphatically *not* SIMT, even when you have predication (which it looks like you're saying that the SMS-05 was designed with?). i will keep looking :) Lkcl (talk) 15:39, 14 April 2025 (UTC)[reply]

the answer is NO. ILLIAC IV or actually SOLOMON was the earliest I could find. Lkcl (talk) 12:11, 25 July 2025 (UTC)[reply]

Same as SPMD

I think this article should either be merged with SPMD, or it should be explained how the two are different. Here's a lecture by a senior computer architect saying that they are synonyms: youtube_com/watch?v=mgtlbEqn2dA&t=808 — Preceding unsigned comment added by 180.150.36.7 (talk) 03:47, 5 October 2019 (UTC)[reply]

ah. right. no, but you raise a really good "differentiator" :) "in SPMD parallel execution, multiple autonomous processors simultaneously execute the same program at independent points," - that is NOT the same as SIMT. SIMT is definitely the instruction being BROADCAST (all processors execute the SAME instruction, because there is only one Program Counter), where SPMD it is very clear that there are MULTIPLE program counters. superb that you brought this up, i'll just do an edit now Lkcl (talk) Lkcl (talk) 15:42, 14 April 2025 (UTC)[reply]

horribly garbled generally

this article is very garbled. ILLIAC IV is very clear. the confusion is down to lack of public information on the internals of secretive modern hardware, trying to claim they are world-first when history says otherwise. Lkcl (talk) 23:08, 25 July 2025 (UTC)[reply]

I added a general "cleanup" tag, best I could find (needs changing?) does the job to warn people that the article is misleading in places and needs work Lkcl (talk) 23:20, 25 July 2025 (UTC)[reply]

ok I am very much done for this editing session. it's better, but even simple programming examples are hard to find that are not overwhelming with CUDA this, HIP that, overhead the other. https://en.m.wikipedia.org/w/index.php?title=Single_instruction%2C_multiple_threads&diff=1302579277&oldid=1302521176 Lkcl (talk) 08:29, 26 July 2025 (UTC)[reply]

original starting paragraph:

Single instruction, multiple threads (SIMT) is an execution model used in parallel computing where single instruction, multiple data (SIMD) is combined with zero-overhead multithreading, i.e. multithreading where the hardware is capable of switching between threads on a cycle-by-cycle basis. There are two models of multithreading involved. In addition to the zero-overhead multithreading mentioned, the SIMD execution hardware is virtualized to represent a multiprocessor, but is inferior to a SPMD processor in that instructions in all "threads" are executed in lock-step in the lanes of the SIMD processor which can only execute the same instruction in a given cycle across all lanes. The SIMT execution model has been implemented on several GPUs and is relevant for general-purpose computing on graphics processing units (GPGPU), e.g. some supercomputers combine CPUs with GPUs.