Draft:Co-Design Automation
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| Company type | Private |
|---|---|
| Headquarters | San Jose, California, United States |
Key people |
|
Co-Design Automation, Inc., was a San Jose, CA, based provider of hardware design and verification language simulation products. Co-Design's main development was the language Superlog that eventually became the IEEE HDL standard SystemVerilog. Co-Design was acquired by Synopsys, Inc. in August 2002.
History
The collaboration that become Co-Design was started in 1995 by Simon Davidmann and Peter Flake working part-time to evolve Hardware Description Language ideas to address limitations in traditional HDL usage for large-scale hardware projects.[1][2][3] During this time there were many other companies competing in language design with Co-Design but Superlog became adopted due to its approach of evolving from the Verilog HDL - the leading design language for digital systems and chips, and solving the evolving new requirements.[4]
The business focus of Co-Design was to build a new language to supersede Verilog HDL and to sell simulation and other tools that supported the language in the same way that Gateway Design had done successfully with Verilog HDL.[4] A key focus was to address the growing need for more efficient verification solutions as hardware designs were getting larger and more complex and Superlog was developed to address this need with many new verification capabilities.[2] The goals were to make the processes of design and verification of digital chips more abstract, efficient and faster to complete.[5]
Founding
Davidmann and Flake had previously worked together at Brunel University in the early 1980s on the development of one of the first HDLs: HILO and in 1995 started collaboration on Superlog leading to the incorporation of Co-Design in 1997.[3]
The founders and management team included:
- Simon Davidmann, CEO and founder
- Peter Flake, CTO and founder
- James Kenney, Chief Engineer
- Dave Kelf, VP Marketing
- Phil Moorby, VP Engineering
References
- ^ Flake, Peter; Moorby, Phil; Golson, Steve; Salz, Arturo; Davidmann, Simon (2020-06-12). "Verilog HDL and its ancestors and descendants". Proc. ACM Program. Lang. 4 (HOPL): 87:1–87:90. doi:10.1145/3386337.
- ^ a b "SystemVerilog for Design". SpringerLink. 2006. doi:10.1007/0-387-36495-1.
- ^ a b Dettmer, R. (2004-08-01). "The HILO inheritance". IEE Review. 50 (8): 22–26. doi:10.1049/ir:20040803. ISSN 0953-5683.
- ^ a b EETimes (2000-11-06). "The Superlog evolution". EE Times. Retrieved 2025-05-29.
- ^ "Co-Design Automation Launches Innovative Product Line to Reshape System Design Methodologies". www.design-reuse.com. Retrieved 2025-05-29.