Successive-approximation ADC

A successive-approximation ADC is a type of analog-to-digital converter (ADC) that digitizes each sample from a continuous analog waveform using a binary search through all possible quantization levels.

Algorithm

The successive-approximation analog-to-digital converter circuit typically contains four chief subcircuits:

A sample-and-hold circuit that acquires the input voltage $V in$ .
An analog voltage comparator that compares $V in$ to the output of a digital-to-analog converter (DAC).
A successive-approximation register that is updated by results of the comparator to provide the DAC with a digital code whose accuracy increases each successive iteration.
A DAC that supplies the comparator with an analog voltage relative to the reference voltage $V ref$ and proportional to the digital code of the SAR.

The successive-approximation register is initialized with 1 in the most significant bit (MSB) and zeroes in the lower bits. The register's code is fed into the DAC, which provides an analog equivalent of its digital code (initially $.mw-parser-output .sfrac{white-space:nowrap}.mw-parser-output .sfrac.tion,.mw-parser-output .sfrac .tion{display:inline-block;vertical-align:-0.5em;font-size:85%;text-align:center}.mw-parser-output .sfrac .num{display:block;line-height:1em;margin:0.0em 0.1em;border-bottom:1px solid}.mw-parser-output .sfrac .den{display:block;line-height:1em;margin:0.1em 0.1em}.mw-parser-output .sr-only{border:0;clip:rect(0,0,0,0);clip-path:polygon(0px 0px,0px 0px,0px 0px);height:1px;margin:-1px;overflow:hidden;padding:0;position:absolute;width:1px}⁠1/2⁠Vref$ ) to the comparator for comparison with the sampled input voltage. If this analog voltage exceeds $V in$ , then the comparator causes the SAR to reset this bit; otherwise, the bit is left as 1. Then the next bit is set to 1 and the same test is done, continuing this binary search until every bit in the SAR has been tested. The resulting code is the digital approximated output of the sampled input voltage.

The algorithm's objective for the $n th$ iteration is to approximately digitize the input voltage to an accuracy of 1⁄2ⁿ relative to the reference voltage. To show this mathematically, the normalized input voltage is represented as $x$ in $[-1, 1]$ by letting $V in = xV ref$ . The algorithm starts with an initial approximation of $x 0 = 0$ and during each iteration $i$ produces the following approximation:

$i th$ approximation: $x i = x i -1 - ⁠ s (x i -1 - x) / 2 i ⁠$

where $s (x)$ represents the operation of the comparator mathematically as a binary signum function: $s(x):={\begin{cases}1&{\text{if }}x\geq 0,\\-1&{\text{if }}x<0.\end{cases}}$ It follows using mathematical induction that the approximation of the $n th$ iteration ideally has a bounded accuracy of: $| x n - x | \leq ⁠ 1 / 2 n ⁠$ .

Inaccuracies in non-ideal analog circuits

When implemented as a real analog circuit, circuit inaccuracies and noise may cause the binary search algorithm to incorrectly remove values it believes $V in$ cannot be, so a successive-approximation ADC might not output the closest value. It is very important for the DAC to accurately produce all $2 n$ analog values for comparison against the unknown $V in$ in order to produce a best match estimate. The maximal error can easily exceed several LSBs, especially as the error between the actual and ideal $2 n$ becomes large. Manufacturers may characterize the accuracy using an effective number of bits (ENOB) smaller than the actual number of output bits.

Examples

Example 1: The ten steps to converting an analog input to 10 bit digital, using successive-approximation, are shown here for all voltages from 5 V to 0 V in 0.1 V iterations. Since the reference voltage is 5 V, when the input voltage is also 5 V, all bits are set. As the voltage is decreased to 4.9 V, only some of the least significant bits are cleared. The MSB will remain set until the input is one half the reference voltage, 2.5 V.

The binary weights assigned to each bit, starting with the MSB, are 2.5, 1.25, 0.625, 0.3125, 0.15625, 0.078125, 0.0390625, 0.01953125, 0.009765625, 0.0048828125. All of these add up to 4.9951171875, meaning binary 1111111111, or one LSB less than 5.

When the analog input is being compared to the internal DAC output, it effectively is being compared to each of these binary weights, starting with the 2.5 V and either keeping it or clearing it as a result. Then by adding the next weight to the previous result, comparing again, and repeating until all the bits and their weights have been compared to the input, the result, a binary number representing the analog input, is found.

Example 2: The working of a 4-bit successive-approximation ADC is illustrated below. The MSB is initially set to 1 whereas the remaining digits are set to zero. If the input voltage is lower than the value stored in the register, on the next clock cycle, the register changes its value to that illustrated in the figure by following the green line. If the input voltage is higher, then on the next clock cycle, the register changes its value to that illustrated in the figure by following the red line. The simplified structure of this type of ADC that acts on $2 n$ volts range can be expressed as an algorithm:

Initialize register with MSB set to 1 and all other values set to zero.
In n-th clock cycle, if voltage is higher than digital equivalent voltage of the number in register, the (n+1)-th digit from the left is set to 1. If the voltage were lower than digital equivalent voltage, then n-th digit from left is set to zero and the next digit is set to 1. To perform a conversion, an N-bit ADC requires N such clock cycles excluding the initial state.

Working of successive approximation ADC

Setup where output values of the ADC are arranged in a grid, vertical axis corresponding to voltage. It is a 4-bit ADC that measures input voltages from 0V to 15V.

Previously established setup where an input voltage of 10.4V is provided.

Previously established setup where an input voltage of 9.4V is provided.

The successive-approximation ADC can be alternatively explained by first uniformly assigning each digital output to corresponding ranges as shown. It can be seen that the algorithm essentially divides the voltage range into two regions and checks which of the two regions the input voltage belongs to. Successive steps involve taking the identified region from before and further dividing the region into two and continuing identification. This occurs until all possible choices of digital representations are exhausted, leaving behind an identified region that corresponds to only one of the digital representations.

Variants

Counter type ADC: The D to A converter can be easily turned around to provide the inverse function A to D conversion. The principle is to adjust the DAC's input code until the DAC's output comes within $\pm 1 ⁄ 2$ LSB to the analog input which is to be converted to binary digital form.
Servo tracking ADC: It is an improved version of a counting ADC. The circuit consists of an up-down counter with the comparator controlling the direction of the count. The analog output of the DAC is compared with the analog input. If the input is greater than the DAC output signal, the output of the comparator goes high and the counter is caused to count up. The tracking ADC has the advantage of being simple. The disadvantage, however, is the time needed to stabilize as a new conversion value is directly proportional to the rate at which the analog signal changes.

Charge-redistribution successive-approximation ADC

One of the most common implementations of the successive-approximation ADC, the charge-redistribution successive-approximation ADC, uses a charge-scaling DAC. The charge-scaling DAC simply consists of an array of individually switched binary-weighted capacitors. The amount of charge upon each capacitor in the array is used to perform the aforementioned binary search in conjunction with a comparator internal to the DAC and the successive-approximation register.

The capacitor array is completely discharged to the offset voltage of the comparator, $V OS$ . This step provides automatic offset cancellation (i.e. the offset voltage represents nothing but dead charge, which can't be juggled by the capacitors).
All of the capacitors within the array are switched to the input signal $V in$ . The capacitors now have a charge equal to their respective capacitance times the input voltage minus the offset voltage upon each of them.
The capacitors are then switched so that this charge is applied across the comparator input, creating a comparator input voltage equal to $- V in$ .
The actual conversion process proceeds. First, the MSB capacitor is switched to $V ref$ , which corresponds to the full-scale range of the ADC. Due to the binary-weighting of the array, the MSB capacitor forms a 1:1 charge divider with the rest of the array. Thus, the input voltage to the comparator is now $- V in + V ref ⁄ 2$ . Subsequently, if $V in$ is greater than V_ref⁄2, then the comparator outputs a digital 1 as the MSB, otherwise it outputs a digital 0 as the MSB. Each capacitor is tested in the same manner until the comparator input voltage converges to the offset voltage, or at least as close as possible given the resolution of the DAC.

References

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