Source-synchronous

When unidirectional data signals timing is referenced to a clock sourced by the same device that generates those signals, and not to a global clock (i.e. generated by a bus master).

Common in high-speed interfaces, including DDR SDRAM interfaces, SGI XIO interface, HyperTransport, SPI-4.2 and many others.

A principal advantage of source-synchronous clocking is that the gates within a given device experience the same process-voltage-temperature (PVT) variation. This means delay experienced by the data through a device tracks the delay experienced by the clock through that same device over PVT. This advantage allows higher speed operation over solutions where the clock is provided from a third device to both the transmitter and the receiver.